mirror of https://github.com/llvm/circt.git
103 lines
3.8 KiB
C
103 lines
3.8 KiB
C
/*===- firtool.c - Simple test of FIRRTL C APIs ---------------------------===*\
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|* *|
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|* Part of the LLVM Project, under the Apache License v2.0 with LLVM *|
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|* Exceptions. *|
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|* See https://llvm.org/LICENSE.txt for license information. *|
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|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* RUN: circt-capi-firtool-test 2>&1 | FileCheck %s
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*/
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#include "circt-c/Firtool/Firtool.h"
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#include "circt-c/Dialect/FIRRTL.h"
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#include "mlir-c/BuiltinAttributes.h"
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#include "mlir-c/BuiltinTypes.h"
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#include "mlir-c/IR.h"
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#include "mlir-c/Pass.h"
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#include "mlir-c/Support.h"
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#include <assert.h>
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#include <stdio.h>
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#include <stdlib.h>
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void exportCallback(MlirStringRef message, void *userData) {
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printf("%.*s", (int)message.length, message.data);
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}
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void exportVerilog(MlirContext ctx, bool disableOptimization) {
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// clang-format off
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const char *testFIR =
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"firrtl.circuit \"ExportTestSimpleModule\" {\n"
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" firrtl.module @ExportTestSimpleModule(in %in_1: !firrtl.uint<32>,\n"
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" in %in_2: !firrtl.uint<32>,\n"
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" out %out: !firrtl.uint<32>) {\n"
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" %0 = firrtl.and %in_1, %in_2 : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32>\n"
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" %1 = firrtl.and %0, %in_2 : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32>\n"
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" firrtl.connect %out, %1 : !firrtl.uint<32>, !firrtl.uint<32>\n"
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" }\n"
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"}\n";
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// clang-format on
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MlirModule module =
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mlirModuleCreateParse(ctx, mlirStringRefCreateFromCString(testFIR));
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MlirPassManager pm = mlirPassManagerCreate(ctx);
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CirctFirtoolFirtoolOptions options = circtFirtoolOptionsCreateDefault();
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circtFirtoolOptionsSetDisableOptimization(options, disableOptimization);
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MlirLogicalResult result =
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circtFirtoolPopulatePreprocessTransforms(pm, options);
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assert(mlirLogicalResultIsSuccess(result));
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result = circtFirtoolPopulateCHIRRTLToLowFIRRTL(
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pm, options, mlirStringRefCreateFromCString("-"));
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assert(mlirLogicalResultIsSuccess(result));
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result = circtFirtoolPopulateLowFIRRTLToHW(pm, options);
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assert(mlirLogicalResultIsSuccess(result));
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result = circtFirtoolPopulateHWToSV(pm, options);
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assert(mlirLogicalResultIsSuccess(result));
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result = circtFirtoolPopulateExportVerilog(pm, options, exportCallback, NULL);
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assert(mlirLogicalResultIsSuccess(result));
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result = circtFirtoolPopulateFinalizeIR(pm, options);
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assert(mlirLogicalResultIsSuccess(result));
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result = mlirPassManagerRunOnOp(pm, mlirModuleGetOperation(module));
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assert(mlirLogicalResultIsSuccess(result));
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}
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void testExportVerilog(MlirContext ctx) {
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exportVerilog(ctx, false);
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// CHECK: module ExportTestSimpleModule( // -:2:3
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// CHECK-NEXT: input [31:0] in_1, // -:2:44
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// CHECK-NEXT: in_2, // -:3:44
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// CHECK-NEXT: output [31:0] out // -:4:45
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// CHECK-NEXT: );
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// CHECK-EMPTY:
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// CHECK-NEXT: assign out = in_1 & in_2; // -:2:3, :5:10, :6:10
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// CHECK-NEXT: endmodule
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exportVerilog(ctx, true);
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// CHECK: module ExportTestSimpleModule( // -:2:3
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// CHECK-NEXT: input [31:0] in_1, // -:2:44
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// CHECK-NEXT: in_2, // -:3:44
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// CHECK-NEXT: output [31:0] out // -:4:45
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// CHECK-NEXT: );
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// CHECK-EMPTY:
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// CHECK-NEXT: assign out = in_1 & in_2 & in_2; // -:2:3, :5:10, :6:10
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// CHECK-NEXT: endmodule
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}
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int main(void) {
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MlirContext ctx = mlirContextCreate();
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mlirDialectHandleLoadDialect(mlirGetDialectHandle__firrtl__(), ctx);
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testExportVerilog(ctx);
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return 0;
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}
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