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AIGToComb
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[AIGToComb] [circt-synth] Add a AIG to Comb conversion pass (#7742)
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2024-10-29 14:15:41 +09:00 |
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AffineToLoopSchedule
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[SSP] Separate `ResourceType` from `OperatorType` (#8444)
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2025-05-13 08:52:11 -04:00 |
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ArcToLLVM
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[LLVM] bump to f87109f018faad5f3f1bf8a4668754c24e84e886 (#8431)
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2025-04-21 09:27:04 -04:00 |
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CFToHandshake
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[CMake] Consistently declare conversion libraries and simplify circt-opt link target list (#7610)
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2024-09-19 20:35:45 +01:00 |
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CalyxNative
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[CMake] Consistently declare conversion libraries and simplify circt-opt link target list (#7610)
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2024-09-19 20:35:45 +01:00 |
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CalyxToFSM
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[CMake] Consistently declare conversion libraries and simplify circt-opt link target list (#7610)
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2024-09-19 20:35:45 +01:00 |
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CalyxToHW
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[CMake] Consistently declare conversion libraries and simplify circt-opt link target list (#7610)
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2024-09-19 20:35:45 +01:00 |
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CombToAIG
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[circt-synth] Lower comb.add to Parallel-Prefix Adder (#8457)
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2025-05-05 13:58:57 -07:00 |
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CombToArith
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[Pass] Remove unnecessary OperationPass<mlir::ModuleOp> (#8116)
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2025-01-23 09:39:34 -08:00 |
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CombToLLVM
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[NFCI][Conversion] Refactor TableGen Pass includes (#7174)
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2024-06-14 16:37:29 +02:00 |
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CombToSMT
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[LLVM] integrate upstream SMT (#8408)
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2025-04-14 14:34:14 -04:00 |
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ConvertToArcs
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Bump LLVM to ebc7efbab5c58b46f7215d63be6d0208cb588192. (#8089)
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2025-01-18 16:05:04 -07:00 |
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DCToHW
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[DC] Initial values were being ignored (#7945)
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2024-12-06 18:24:35 -05:00 |
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ExportChiselInterface
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[NFCI][Conversion] Refactor TableGen Pass includes (#7174)
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2024-06-14 16:37:29 +02:00 |
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ExportVerilog
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[FIRRTL][SV] Add fflush operation (#8420)
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2025-04-17 19:06:22 -07:00 |
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FIRRTLToHW
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[LowerToHW] Emit an error when $fopen failed for FD lowering (#8511)
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2025-05-22 14:44:10 -07:00 |
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FSMToSV
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[NFCI][Conversion] Refactor TableGen Pass includes (#7174)
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2024-06-14 16:37:29 +02:00 |
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HWArithToHW
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[HWArith] Fix lowering to HW with type aliases
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2024-12-19 00:57:08 +00:00 |
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HWToBTOR2
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Drop unneeded headers (#8433)
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2025-04-22 07:46:35 -07:00 |
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HWToLLVM
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Bump LLVM (#7223)
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2024-06-26 13:19:37 -07:00 |
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HWToSMT
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[LLVM] integrate upstream SMT (#8408)
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2025-04-14 14:34:14 -04:00 |
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HWToSV
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[NFCI][Conversion] Refactor TableGen Pass includes (#7174)
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2024-06-14 16:37:29 +02:00 |
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HWToSystemC
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[NFCI][Conversion] Refactor TableGen Pass includes (#7174)
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2024-06-14 16:37:29 +02:00 |
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HandshakeToDC
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[DC] Initial values were being ignored (#7945)
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2024-12-06 18:24:35 -05:00 |
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HandshakeToHW
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Bump LLVM to 3cc852ece438a63e7b09d1c84a81d21598454e1a. (#7847)
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2024-11-21 20:15:27 -07:00 |
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ImportVerilog
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[Moore] Add `moore.string_cmp` op (#8447)
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2025-05-01 08:54:38 -07:00 |
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LTLToCore
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[NFC][LTLToCore] Fix incomplete comment
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2025-02-04 16:51:15 +00:00 |
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LoopScheduleToCalyx
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Bump LLVM to c6c2e21028cadef854cf22f6ecaa5eb9d224b76d. (#8467)
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2025-05-06 09:07:04 -06:00 |
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MooreToCore
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[MooreToCore] Lower `moore.array_create` op (#8364)
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2025-04-02 13:18:36 -07:00 |
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PipelineToHW
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[Pipeline] Make `reset` signal optional (#8104)
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2025-01-23 14:15:50 +01:00 |
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SCFToCalyx
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[circt-opt][Calyx] Integrate the Math to `circt-opt` and lower `math.sqrt` to Calyx (#8475)
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2025-05-11 13:02:19 -04:00 |
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SMTToZ3LLVM
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[LLVM] bump to f87109f018faad5f3f1bf8a4668754c24e84e886 (#8431)
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2025-04-21 09:27:04 -04:00 |
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SeqToSV
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[FirRegLowering] Add limit to number of ifs generated (#8313)
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2025-04-02 12:30:55 -04:00 |
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SimToSV
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SimToSV: Keep plusargs non-synth === under !SYNTHESIS block (#8478)
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2025-05-15 16:13:22 -07:00 |
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VerifToSMT
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[circt-lec] Implement emit-smtlib functionality for circt-lec (#8497)
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2025-05-22 15:26:10 +01:00 |
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VerifToSV
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[Verif] disambiguate ctor (#8076)
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2025-01-13 12:33:10 -05:00 |
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CMakeLists.txt
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[AIGToComb] [circt-synth] Add a AIG to Comb conversion pass (#7742)
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2024-10-29 14:15:41 +09:00 |
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