mirror of https://github.com/llvm/circt.git
317 lines
8.0 KiB
C++
317 lines
8.0 KiB
C++
//===- RTGTest.cpp - C interface for the RTGTest dialect ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "circt-c/Dialect/RTGTest.h"
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#include "circt/Dialect/RTGTest/IR/RTGTestAttributes.h"
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#include "circt/Dialect/RTGTest/IR/RTGTestDialect.h"
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#include "circt/Dialect/RTGTest/IR/RTGTestTypes.h"
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#include "mlir/CAPI/Registration.h"
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using namespace circt;
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using namespace circt::rtgtest;
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//===----------------------------------------------------------------------===//
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// Dialect API.
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//===----------------------------------------------------------------------===//
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MLIR_DEFINE_CAPI_DIALECT_REGISTRATION(RTGTest, rtgtest, RTGTestDialect)
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//===----------------------------------------------------------------------===//
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// Type API.
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//===----------------------------------------------------------------------===//
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bool rtgtestTypeIsACPU(MlirType type) { return isa<CPUType>(unwrap(type)); }
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MlirType rtgtestCPUTypeGet(MlirContext ctxt) {
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return wrap(CPUType::get(unwrap(ctxt)));
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}
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bool rtgtestTypeIsAIntegerRegister(MlirType type) {
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return isa<IntegerRegisterType>(unwrap(type));
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}
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MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt) {
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return wrap(IntegerRegisterType::get(unwrap(ctxt)));
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}
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//===----------------------------------------------------------------------===//
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// Attribute API.
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//===----------------------------------------------------------------------===//
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bool rtgtestAttrIsACPU(MlirAttribute attr) {
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return isa<CPUAttr>(unwrap(attr));
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}
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MlirAttribute rtgtestCPUAttrGet(MlirContext ctxt, unsigned id) {
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return wrap(CPUAttr::get(unwrap(ctxt), id));
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}
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unsigned rtgtestCPUAttrGetId(MlirAttribute attr) {
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return cast<CPUAttr>(unwrap(attr)).getId();
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}
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// Registers
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//===----------------------------------------------------------------------===//
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bool rtgtestAttrIsARegZero(MlirAttribute attr) {
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return isa<RegZeroAttr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegZeroAttrGet(MlirContext ctxt) {
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return wrap(RegZeroAttr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegRa(MlirAttribute attr) {
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return isa<RegRaAttr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegRaAttrGet(MlirContext ctxt) {
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return wrap(RegRaAttr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegSp(MlirAttribute attr) {
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return isa<RegSpAttr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegSpAttrGet(MlirContext ctxt) {
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return wrap(RegSpAttr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegGp(MlirAttribute attr) {
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return isa<RegGpAttr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegGpAttrGet(MlirContext ctxt) {
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return wrap(RegGpAttr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegTp(MlirAttribute attr) {
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return isa<RegTpAttr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegTpAttrGet(MlirContext ctxt) {
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return wrap(RegTpAttr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT0(MlirAttribute attr) {
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return isa<RegT0Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT0AttrGet(MlirContext ctxt) {
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return wrap(RegT0Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT1(MlirAttribute attr) {
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return isa<RegT1Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT1AttrGet(MlirContext ctxt) {
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return wrap(RegT1Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT2(MlirAttribute attr) {
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return isa<RegT2Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT2AttrGet(MlirContext ctxt) {
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return wrap(RegT2Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS0(MlirAttribute attr) {
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return isa<RegS0Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS0AttrGet(MlirContext ctxt) {
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return wrap(RegS0Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS1(MlirAttribute attr) {
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return isa<RegS1Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS1AttrGet(MlirContext ctxt) {
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return wrap(RegS1Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA0(MlirAttribute attr) {
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return isa<RegA0Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA0AttrGet(MlirContext ctxt) {
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return wrap(RegA0Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA1(MlirAttribute attr) {
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return isa<RegA1Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA1AttrGet(MlirContext ctxt) {
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return wrap(RegA1Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA2(MlirAttribute attr) {
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return isa<RegA2Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA2AttrGet(MlirContext ctxt) {
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return wrap(RegA2Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA3(MlirAttribute attr) {
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return isa<RegA3Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA3AttrGet(MlirContext ctxt) {
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return wrap(RegA3Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA4(MlirAttribute attr) {
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return isa<RegA4Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA4AttrGet(MlirContext ctxt) {
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return wrap(RegA4Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA5(MlirAttribute attr) {
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return isa<RegA5Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA5AttrGet(MlirContext ctxt) {
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return wrap(RegA5Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA6(MlirAttribute attr) {
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return isa<RegA6Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA6AttrGet(MlirContext ctxt) {
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return wrap(RegA6Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegA7(MlirAttribute attr) {
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return isa<RegA7Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegA7AttrGet(MlirContext ctxt) {
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return wrap(RegA7Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS2(MlirAttribute attr) {
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return isa<RegS2Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS2AttrGet(MlirContext ctxt) {
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return wrap(RegS2Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS3(MlirAttribute attr) {
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return isa<RegS3Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS3AttrGet(MlirContext ctxt) {
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return wrap(RegS3Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS4(MlirAttribute attr) {
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return isa<RegS4Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS4AttrGet(MlirContext ctxt) {
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return wrap(RegS4Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS5(MlirAttribute attr) {
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return isa<RegS5Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS5AttrGet(MlirContext ctxt) {
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return wrap(RegS5Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS6(MlirAttribute attr) {
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return isa<RegS6Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS6AttrGet(MlirContext ctxt) {
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return wrap(RegS6Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS7(MlirAttribute attr) {
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return isa<RegS7Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS7AttrGet(MlirContext ctxt) {
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return wrap(RegS7Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS8(MlirAttribute attr) {
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return isa<RegS8Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS8AttrGet(MlirContext ctxt) {
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return wrap(RegS8Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS9(MlirAttribute attr) {
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return isa<RegS9Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS9AttrGet(MlirContext ctxt) {
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return wrap(RegS9Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS10(MlirAttribute attr) {
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return isa<RegS10Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS10AttrGet(MlirContext ctxt) {
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return wrap(RegS10Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegS11(MlirAttribute attr) {
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return isa<RegS11Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegS11AttrGet(MlirContext ctxt) {
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return wrap(RegS11Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT3(MlirAttribute attr) {
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return isa<RegT3Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT3AttrGet(MlirContext ctxt) {
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return wrap(RegT3Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT4(MlirAttribute attr) {
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return isa<RegT4Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT4AttrGet(MlirContext ctxt) {
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return wrap(RegT4Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT5(MlirAttribute attr) {
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return isa<RegT5Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT5AttrGet(MlirContext ctxt) {
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return wrap(RegT5Attr::get(unwrap(ctxt)));
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}
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bool rtgtestAttrIsARegT6(MlirAttribute attr) {
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return isa<RegT6Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestRegT6AttrGet(MlirContext ctxt) {
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return wrap(RegT6Attr::get(unwrap(ctxt)));
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}
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