Fix a bug in the parser where a DontTouchAnnotation on a subfield would
not cause names to be preserved. Use the simplest solution here of
using the hasDontTouch method of AnnotationSet as opposed to the older
version of the method of the same name in the parser. Remove the old
hasDontTouch method in the parser (since this is now unused).
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Adds emitters for: RegisterOp, MemoryOp, GroupGoOp, GroupDoneOp, SeqOp,
WhileOp, IfOp, EnableOp, combinational guards. Remove HasParent trait from
MemoryOp since this is checked by the Cell trait (inherited by CalyxCell). Move
base class for CalyxPrimitive to CalyxPrimitives.td. Add helper functions for string
literals. Add simple emitter for imports.
Add a check that the foldResetMux rewrite pattern isn't used for
firrtl.regreset if the reset has a DontTouchAnnotation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add the `DataTapTests` from the Scala implementation of FIRRTL as an
integration test for the FIRRTL dialect. This uncovers a few subtle
breakages in the `GrandCentralTaps` introduced by changes to the
annotation scattering code that happened a while back. This fixes those
issues and the test ensures we don't have any regressions of this in the
future.
This makes lookup much faster, even though it still requires IR scanning.
This speeds up `firtool -extract-test-code -verilog` on a large design from
550s to 120s. There is still more to go though, as a -verify-each=false
run completes in 60s - we're still spending more time verifying than doing
work.
This resolves issue #1647.
This is the first step to supporting verilog implementations like Yosys
and Icarus Verilog that don't support SystemVerilog "automatic logic"
variables in procedural scopes.
For this step we handle side effecting operations (like the RANDOM
macros in FIRRTL lowering) by spilling them to a local reg with a
blocking assignment, the same way SFC does.
This is one step towards resolving Issue #1633
FIRRTL files coming out of chisel don't seem to preserve module
locations typically even though they could, but other clients can
produce location info for them, and we should print it.
It turns out that sv.bind can exist inside of a hw.module as well
as at the top level. These cause non-local references so we need
to make sure not to emit such modules concurrently with the modules
being emitted.
There is no good test for this, I noticed it due to a transient
failure of the existing ExportVerilog/sv-dialect.mlir test.
Using an `int32_t` to parse vector types limits our maximum vector
length to 2147483647. We have memory length 1 higher than that maximum,
and we need to use the `int64_t` parser to support it.
getReferencedModule is a performance tarpit because it has to scan the top
level of the circuit to find the right module. We already have the
instance graph, we should use it for all lookups.
This speeds up IMConstProp on a large testcase from 24s to 6.3s.
* [Handshake] Refactor handshake tablegen files
No functional changes; this commit creates an identical structure to the rest of the dialects in CIRCT wrt. how and where the various TableGen'erated files are included.
This parallelizes emission of operations when they are all emitted
to the same file by emitting to string buffers, then concatenating
them all at the end in series (simple map+reduce).
This speeds up emission of a large testcase on my laptop from 17s
to 5.2s, a 3.2x speedup.
This makes it part of the parallel emission when emitting split files,
and avoids having to keep the `ModuleNameManager` in memory for every
module in the circuit before emitting each file. This speeds up
split-verilog emission on a large design from 8.3s to 5.8s (~30%).
Previously all the extracted assert/assume modules were put at the top of the
file. This is a problem because the #ifdef boilerplate needs to come first.
This builds a SymbolCache at setup time, when the verilog exporter
is scanning the ops to see what files they go into. This cache is
then used when emitting each of the chunks, speeding up the
"getReferencedFoo" calls by turning them into O(1) lookups.
This speeds up export verilog on a large testcase that includes a
bunch of binds from 126s to 17s. It should also help speedup
other normal cases as well, since each instance has to resolve the
module it refers to.
The HW/SV dialects have a bunch of symbols used to map instances, modules,
interfaces etc, and corresponding "getReferencedXXX" methods to resolve
them. Each of these resolutions is really slow - scanning huge amounts of
the IR to resolve them, so we should have a way to shortcut that when a
client has done a prepass. The SymbolCache class allows making these faster.
This patch introduces the new functionality, but no clients of it.
Most of the FIRRTL code base expects port annotations to live in the
`portAnnotations` attribute on `FModuleOp` and `FExtModuleOp`. But the
parser, printer, and some operation builders accidentally store these in
`arg_attrs` through the standard argument attribute mechanism of MLIR.
This commit removes redundant/conflicting uses of `arg_attrs` and
`portAnnotations` in the code base. To keep things ergonomic for the
custom syntax of FIRRTL operations, we still parse and print port
annotations as part of the regular argument attributes (under the
`firrtl.annotations` key), but then immediately separate them out into
the `portAnnotations` attribute where all of our code expects this to
live.
Just pass down the output filename instead of a lambda, there is no
need for the extra abstraction here. While here, change the timer
in the various flavors of output to be more specific than "Output".
Anurudh Peduri