Adds a moduleop to the MSFT dialect. For now, it's mostly like hw.module but adds parameters to represent the specific parameterization of a parameterized module. Also necessarily adds a msft.output since hw.output expects to be in a hw.module.
Step 3 of #1755.
This adds the prefix-modules pass to FIRRTL. This pass looks for
modules annotated with the `NestedPrefixModulesAnnotation` and prefixes
the names of all modules instantiated underneath it. This pass will
duplicate modules as necessary to give submodules unique names. The
annotation can be attached to module definitions, as well as specific
instances.
The supported annotation is:
```json
{
class = "sifive.enterprise.firrtl.NestedPrefixModulesAnnotation",
prefix = "MyPrefix_",
inclusive = true
}
```
If `inclusive` is false, it will not attach the prefix to target module,
only to modules instantiated underneath it.
There was nothing forcing these ports to be overdefined before, so constants could leak through.
The undefined flag gets propagated to the instance port moments later.
One could remove the don't touch check in visitConnect now, but it's not clear if checking the attributes is cheaper than merging some lattice values.
Remove a lot of assertions and checks that are validated by the ODS and `verifyInstanceOp` function. Secondly,
use SymbolOpUserInterface in MSFT dialect to avoid O(n) lookup when verifying the InstanceOp.
Prefix the attribute `DesignUnderTest` with `firrtl` since it defines a `FIRRTL` specific property.
Update the docs and tests accordingly.
Followup to commit #805d7e8be89524f53bf30895469ee78408ea1f6b
This makes both hw.module* and hw.instance carry an argNames/resultNames
array attribute for the port names, and the verifier checks that they
line up.
This makes various queries on the instances much much faster (because
you don't need to resolve the module being referenced) and makes the
code more obviously correct in multithreaded situations.
warning: object backing the pointer will be destroyed at the end of the full-expression [-Wdangling-gsl]
StringRef portName = valueName(group->getParentOfType<ComponentOp>(), value);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The annotation `sifive.enterprise.firrtl.MarkDUTAnnotation` , marks what is the DUT (and not the testbench).
Lower the annotation, to the attribute "DesignUnderTest", during `LowerToHW`.
Adds attribute `{DesignUnderTest }` to the module which has this annotation.
Other `sv/hw` passes can use this attribute to identify the DUT.
This adds a combinational trait to Calyx operations. We can throw this on all non-memory operations for now,
since they are all combinational. Eventually we'll need to split this off. Closes#1739. Also fixes a bug where it
was considering a memory load as a store, since the address ports are used when both storing and loading to
a MemoryOp. A test is added to verify this no longer occurs.
As discussed in #1769, some verifiers should be added to avoid giving the sources of group ports / assignments
logically complex expressions. Also adds a verifier to ensure that GroupOp isn't being used as a CombGroupOp, and
makes the necessary refactoring. This will be removed when native Calyx supports complex arguments for sources.
This PR focuses on (2) objectives. First, verifying that combinational groups are indeed combinational.
Combinational components are not supported yet, so component instances are always assumed to be
combinational for now. Second, we also verify that certain ports are written or read together. For example,
it does not make sense to write to a register without write_en being high. To aid in this, I added helper
functions to access certain ports on primitive operations.
Add an integration test of Grand Central Views that uses Verilator to
lint and type-check the produced SystemVerilog output. This is
primarily done to test the following features:
- All necessary interfaces are generated
- All XMRs are valid (XMRs use the correct instance names)
Both single file ("firtool -verilog") and multi-file output ("firtool
-split-verilog" with an annotation file doing extraction) are tested.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Mux is the only normal operation that even has 3 operands, so narrow these small vectors.
Save a few bytes not having a local mutable array of strings.
Fix more ESI tests and integration tests to use the new HW dialect
module/instance foramt.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Switch from a two-dimensional interface in the Grand Central View
interface integration test to a one-dimensional interface. Do this so
that Verilator can type-check and lint the output Verilog. (Verilator
does not support multi-dimensional interfaces.)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This updates LLVM to 704a395. We are pulling the new version of LLVM for the top commit which allows 0-bit APInts. This will help us model 0 bit constants in FIRRTL, and we will be able to properly use IntegerAttr as a (possibly 0-length) bitvector for FIRRTL port directions.
Included in this update is a change to the way `unrealized_conversion_casts` are handled by the LLVM converter infrastructure. We needed to update `LLHDToLLVM` to apply the new conversion casts. For more information see the public PSA on the LLVM discourse[^0].
This revealed a problem in the `LLHDToLLVM` where there was a failed to legalize operations in the lowering of `llhd.proc` and `llhd.entity`. These operation's lowering logic needed to ensure that operations from the (old) body of `llhd.proc` and `llhd.entity` were type converted before inserting new LLVM operations which used their results.
[0] https://llvm.discourse.group/t/psa-run-reconcile-unrealized-casts-after-all-convert-to-llvm-from-now-on/4266
Co-authored-by: Martin Erhart <maerhart@outlook.com>
It is imperative that instance and modules line up w.r.t. types and
port declarations. ESI is (ab)using flexibility in extern modules,
so this doesn't tighten it up all the way, I will file an issue.
This pulls the port names and port types inline into the argument list,
and adds result port names to the output signature. This increases readability
and is a stepping stone to hw.instance maintaining its own port names.
Build break since inline {} doesn't work when multiple builders are present.
Test break since new convenience builders don't work for external parameterized
modules.
Chris Lattner