Previously DPICallLowering called `rewriter.replaceAllUsesWith` for individual
results but it seems that is not equivalent to `replaceOp`.
This also adds missing dialect dependency to seq
Close#7191
This adds `StmtExprVisitor` struct for visitor to handle operations with an optional result. Currently `GenericIntrinsicOp `and `DPICallIntrinsicOp` are added.
Besides that `ExpandWhens` is modified to handle DPI intrinsic.
* Fix paths in tests for windows builds
* Fix patterns that check mlir: backslashes are rendered as double backslashes
* Fix fir emitter for output dirs with backslashes
* Try fixing patterns, again
* FIRLexer: parse escaped backslashes in strings
* Fix more patterns with backslashes
* This time, for an absolute path
This PR introduces a PrepareForFormal pass that tries to alleviate some of the heavy lifting being done in the btor emission. For now this only flattens wires, but in the future in will also handle formal contracts and anything else that is done to make emission for formal tools easier, which is why it's part of the verif dialect and not hw.
This is derived from #7150
* Add getDirectoryAttr helper to HWOutputFileAttr
This helper gets the directory component of an output file name, or returns
nullptr if there is none.
* Output directory control v2
Instead of using an explicit precedence declaration anno to help guide the
assignment of floating modules to output directories, use the directory
hierarchy itself. So if a module is used under directory A/B and A/C, it will
be placed into directory A.
* Support absolute output directories for modules
* Add comment
* Make it so output dir annos only apply to public modules
* Simplify lower layers
* Add ability to configure the output directory of assign-output-dirs
* Update tests
* Address review comments
* Clean up whitespace in test
* clang-format
* Fix up firtool integration test excercising dedup + output dirs
* Address review comments
* [mooretocore] Support namedconstant
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
* Limit type to integertype.
* add mooretocore support
* remove include
* remove verify of hwops
* remove include
* Test added.
* Add test for MooreToCore
* Support any attribute
* Modify test.
* Add symbol for wireOp
* Remove useless include
* Add more test and error cases
* slang-tidy
* some Imporvement
* Improved version
* little change
* Imporve
---------
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
Add a new CombDataflow op interface to FIRRTL.
This interface is used for specifying the combinational dataflow that exists in
the results and operands of an operation. Any operation that doesn't implement
this interface is assumed to have a combinational dependence from each operand
to each result.
Currently only FIRRTL register and memory ops implement this interface, but it
can be used in other dialects that intend to use the CheckCombCycles pass.
This PR modifies ExportVerilog to emit two state types (`bit` in general) for DPI import op. Furthermore, for specific bit width (8, 16, 32 and 64) it emits C-types (byte, shortint, int and longint).
This PR also rejects small integer types other than 8, 16, 32 and 64 bit width since otherwise we have to use`bit` but they are passed by references in DPI. So this PR defines the ABI as "small integers are passed by values, and larger integers are passed by references.
This PR adds DPICallIntrinsicOp and its lowering pass. DPICallIntrinsicOp is lowered into sim.func.dpi.call and sim.func.dpi ops. At FIRRTL level DPICallIntrinsicOp doesn't have symbols and instead LowerDPI pass accumulates call sites and creates symbols for dpi functions. LowerDPI pass directly lowers FIRRTL intrinsic into Sim dialect since FIRRTL doesn't have DPI/Function construct. LowerDPI pass could be simplified (or migrated into LowerToHW) once FIRRTL gets 1st class support for Function. Unrealized conversion cast is used to mix FIRRTL and HW type values before LowerToHW.
ODS InterfacePass generates `canScheduleOn` method with a specified interface in a header file and currently we import every pass declaration through PassesDetail.h. Gcc/clang seem to compile when there is an unknown interface class but MSVC emits an error. So this PR avoids `InterfacePass` in ODS and manually implements `canScheduleOn` in PrepareForEmission.
This PR adds DPI func/call op and SimToSV lowering.
`sim.dpi.func` is a just bridge to `sv.func`. This op can be lowered into `func.func` in the future for Arc integration.
`sim.func.dpi.call` represents SystemVerilog DPI function call. There are two optional operands `clock` and `enable`.
If `clock` is not provided, the callee is invoked when input values are changed. If provided, the dpi function is called at clock's posedge. The result values behave like registers and the DPI function is used as a state transfer function of them. `enable` operand is used to conditionally call the DPI since DPI call could be quite more expensive than native constructs. When `enable` is low, results of unclocked calls are undefined and in SV results they are lowered into `X`. Users are expected to gate result values by another `enable` to model a default value of results. For clocked calls, a low enable means that its register state transfer function is not called. Hence their values will not be modify in that clock.
A function that returns an explicit return is not supported yet.
This commit adds the DUT module instance path to the to the `SiFive_Metadata`
class. This is required to generate the DUT instance path directly from the
OMIR. This will be required to generate DUT relative hierarchy paths for
memories in the seq_mems.json metadata, Since all paths are by default
generated relative to the top level.
This commit creates a list of paths, to handle multiple DUTs even though the
current designs will have a unique DUT.
Bump minimum supported FIRRTL to 2.0.0.
"FIRRTL version" is now required as a result.
Remove parsing of the FIRRTL partial connect operator ("<-"). This has,
for a very long time, been almost unreachable from Chisel-emitted FIRRTL
and is now impossible to emit from Chisel. This has also been completely
removed from the FIRRTL spec in version 2.0.0.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Taps (using probes) support a non-passive source with a passive sink (by their nature), but the hidden option to avoid probes does not.
Detect this specifically and fix by using passive type for wiring from source.
This allows taps of non-ground (non-passive) that work with probes to also work with this option.
* [MooreToCore] Add conversion support for SVModuleOp and InstanceOp
* Trailing newline fix
* Add Fixme
* [MooreToCore] Add a new test case for svmoduleOp and instanceOp
This is a rather crude version without assignOp, variableOp and netOp in the examples.
We generally type-erase objects at the boundary, to avoid needing to
declare the objects' classes as part of the interface. This adds a
cast for the metadataObj reference, so we don't have to declare its
class as part of the interface. The evaluator and any tooling built on
it already know how to "see through" this cast.
... while factoring out `InnerSymbol`+name logic into a new interface that is also used by Ibis port-like ops. This model could probably be factored into the `hw` dialect, seeing as we're also eventually going to divorce symbol names and actual names in `hw.module`.
Also adds de-aliasing logic to `ContainersToHW`, which is required given that `hw.module` doesn't yet split its symbol and name (#7023).
This PR implements ExportVerilog support of sv.func, sv.func.dpi.import, sv.func.call and sv.func.call.procedural.
sv.func emission is similar to hw.module but one difference is a return value. Surprisingly in SV a function name is used as a placeholder for a return value so name legalization properly sets `hw.verilogName` of a returned value to a function name.
Result names of sv.func.call.procedural are attached to temporary registers created in PrepareForEmission. This is similar implementation approach to hw.instance.
Hideto Ueno