The two CHIRRTL memory operations have been renamed from `smem` to
`seqmem` and `cmem` to `combmem`. In addition, instead of returning
`!firrtl.vector<>` types, they return a new type `!firrtl.cmemory`.
This new type can only be used with CHIRRTL memories and ports, and
prevents some shenanigans where it could be used like a normal vector.
Memory ports in SFC are allowed to be used outside of the scope which they are
defined in. To work around this issue, the memory port declaration was split
into two operations:
1. `firrtl.memoryport`: This operation is the declaration of the memory port,
and it should be emitted into the body of the module.
2. `firrtl.memoryport.acccess`: This operations is emitted to the location of
the original memory port declaration, and is used for enable inference.
For more information about these new operations, and why we added them, see the
changes to FIRRTLRational.md.
This include changes to the FIR parser to emit these new operations.
Change FIRRTL dialect folders to use the Scala FIRRTL Compiler (SFC)
interpretation of invalid. An invalid involving a non-mux primitive
operation is treated as a constant zero. An invalid involving the true
or false paths of a multiplexer is treated as a conditionally valid
expression which always evaluates to the non-invalid path.
This intentionally deviates from the FIRRTL spec interpretation of
invalid as undefined behavior. Invalidations are frequently generated
by Chisel (as a means of telling the SFC that an uninitialized component
is okay) and by a legacy version of Chisel ("Chisel 2 Compatibility
Mode") which defaults all connections to invalid to permanently disable
uninitialized checking.
Concretely, this adds the following boolean folds:
- or(a, invalid) -> a
- or(invalid, a) -> a
- xor(a, invalid) -> a
- xor(invalid, a) -> a
The following boolean folds already existed, but are documented with
information about the SFC interpretation of invalid:
- and(a, invalid) -> 0
- and(invalid, a) -> 0
Invalid value folders are also added for the following arithmetic
operations:
- add(x, invalid) -> bits(x, width)
- sub(x, invalid) -> bits(x, width)
- mul(x, invalid) -> 0
- div(invalid, x) -> 0
- rem(invalid, x) -> 0
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This moves the annotation documentation out of the FIRRTL rational and in to its own document. It expands the target section a little bit with some details from a Google Docs document. At the end of the document is reference style material for each annotation. This works pretty well for the simple annotations, but for GrandCentral each annotation had to have several tables to describe the format. Details were collected from the Scala source code and our tests.
The Scala format specifier was previously used to get decent highlighting for FIRRTL code, but this does not render well on the CIRCT website.
* Add a `verbatim.expr` operation to the FIRRTL dialect which lowers to
the corresponding operation in the SV dialect. This allows
construction of FIRRTL-typed expressions from a string representation.
* Based on a suggestion by @lattner in #1178.
This makes sure not to rename FIRRTL to HWRTL :-), and I spot checked a
many things to avoid changing general references to RTL (e.g. when referring
to external tools) but I suspect that I missed some. Please let me know (or
directly correct) any mistakes in this mechanical patch.
Update the FIRRTL Rationale document with information regarding the
change of direction to align closely with FIRRTL IR and the Scala FIRRTL
Compiler, i.e., type canonicalization was removed and input/output are
no longer encoded using flip type.
Add a new section on Annotations, Targets, and the status/plan with
respect to Annotation migration.
Cleanup miscelaneous things:
- 80 character columns
- Use scala code fence modifier for FIRRTL IR code (this works pretty
well for syntax highlighting)
- Add more info on how invalid is blown out during parsing
- Use "ANTLR" instead of "Antlr"
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Remove the `validif` operation from the IR and replace any occurrences
during parsing with an equivalent `invalidvalue` and `mux` operation.
Fixes#886.
* Adjust a few of the test cases, especially around memories, which do
not run canonicalization and thus no longer see the removal of validif
happen automatically.
Since wires have a duplex type, they can appear on the RHS or LHS of a
connect statement, regardless of whether or not they are a passive type.
When lowering a bulk connect statement involving a wire (i.e.
connecting a bundle type), we need to make sure that the non-duplex type
is used to set the direction of the flow. When doing a bulk connect of
two wires, it is considered an ambiguous flow and an error. To connect
two wires, each field must be connected individually, which is
considered a mono-connection with explicit flow from the RHS to the LHS.
This change adds a function to determine if a value comes from an
expression with duplex flow. This property is transitive through
subfield accesses.
This matches the expectation of the SFC compiler, and LowerTypes/LowerToRTL
require this.
This patch xfails the HandshakeToFIRRTL/test_load.mlir test, which is tracked
in Issue #534.
Previously we followed the same representation as the Scala FIRRTL
implementation, but it is much easier to work with and result in less
IR for us to use multiple-result values.
Add information related to: (1) type canonicalization resulting in
CIRCT accepting more circuits than the SFC, (2) representing kind and
flow information about ports and instances in the types, and (3) minor
cleanup.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This implements the approach described in Issue #324, whereby we turn
flip(analog) into analog. Analog types in FIRRTL are implicitly
bidirectional already, so an "output port of analog type" doesn't
actually make sense. This canonicalization defines away certain
defensive code and eliminates the need for "AsPassive" to apply to
values of analog type.
The FIRRTL version of the verilog printer now prints analog ports as
inputs, if someone cared we could make it properly print inout for
them.
This makes the FIRRTL dialect easier to work with (e.g. the "merge" inference
algorithm in LowerToRTLModule works with invalid now), allows more wire
promotion, opportunities and doesn't affect expressive potential.
This is a deviance from the design explained in the FIRRTL spec so I added a
new section to the rationale to describe it.
Andrew Young