Another step towards #2365. This pass 'bubbles up' wires which are merely pass throughs in a given module. It then 'sinks down' wires which are looped back in the instantiation. Together with the entity movement piece, this effectively moves the wires as well. Does not handle wire manipulation operations, which also need to be moved/copied.
The design partitioning pass used to build HWModuleOps. The new wire
cleanup passes, however, will be operating on the design partitions so
the modifying extensions will come in handy.
In aggregate preservation mode, GrandCentral may create VerbatimExpr ops
with aggregate types. This commit allows verbatim to have non-integer types
such as a struct type or array type.
Change Namespace.h to use a single, unified StringMap instead of a
StringSet and a StringMap. This removes storage of duplicate keys in
two equivalent datstructures.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit adds new operation `multibit_mux` to make
subaccess lowering more efficient. Subaccess ops are
currently lowered into mux chains but in HW/Comb dialect
they are pulled back to `array_create` + `array_get`.
`multibit_mux` will be directly lowered into `array_create`
+ `array_get` at LowerToHW.
This commit containts parser/printer, folder, LowerTypes
and LowerToHW change. `multibit_mux` operations are
created only at subaccess lowering in LowerTypes.
This speeds up entire process after LowerTypes 5%~10%
for large circuits.
This refactors ExportQuartusTcl to use the hw::GlobalRefs and arrays
of hw::InnerRefAttrs directly. This greatly simplifies the
implementation, and removes the need for SwitchInstanceAttr. That
attribute will be fully removed in a follow up.
Add a new operation `GlobalRef` to `HW` dialect, that will eventually replace
`FIRRTL::NonLocalAnchor`.
`GlobalRef` can be used to identify a unique instance path of an operation globally.
This is part of the plan to move the `firrtl.nla` to `HW` dialect.
This commit modifies the creation of new names to skip already used
ones. This fixes regression of LowerToHW caused by many creations of
RANDOM values.
This adds the necessary support to lower single affine loops to
pipelines. Broadly, this encompasses lowering affine structures like
if conditions into arithmetic, and building pipeline stages for each
scheduled group.
This is useful to transformations that want to be able to reuse the
analysis during progressive lowering. If an affine.load or
affine.store is lowered, this API can be used to maintain any
dependences on the replacement op.
Long overdue - buffer insertion is not inherently tied to StandardToHandshake.
- Changed the name from `handshake-insert-buffer` to `handshake-insert-buffers`
- Removed the option of providing multiple buffer strategies at once - I've never seen it used in practice, and there are no guarantees provided for how multiple strategies are supposed to composed if provided at once. I think it's a better option to only allow a single strategy and then, if the user wants to, they can compose strategies manually through subsequent invocations of `handshake-insert-buffers`.
Move the FIRRTL utility "BaseNamespace" to Support and rename it
"Namespace". This class is generally useful for any dialect or
conversion which needs to generate names on the fly.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
The "design partition" feature supports scenarios wherein the designer needs the RTL output module hierarchy to be different than the logical hierarchy they are designing. With this feature, they just create a design partition then "tag" various entities with it. Upon compilation, CIRCT will refactor the hierarchy to move the tagged entities into the specified target partition. The design partition _must_ be found in the module hierarchy above (or in the same module as) the tagged entities.
Partial progress towards #2365.
- Modeling in CIRCT and PyCDE
- Move entities in the same module as the partition
This commit defines a ChainingProblem, which models the accumulation of physical propagation delays on combinational paths along SSA dependences within a scheduling problem's abstract time steps/cycles.
This commit adds `preserve-aggregate` flag to enable experimental
feature to preserve passive aggregate wires/register/connection.
Currently, if preserve-aggregate flag is enabled, we change the
behavior of `peelTypes` function. We don't preserve aggregate if any
of the following condition holds:
1. They are ports of MemOp (Ports of MemOp must be ground types)
2. They are non-passive types
3. They contain an analog type
4. They are types with zero width.
This strategy simply combines the cycles and all strategies, using sequential buffers to break cycles, and transparent FIFO buffers on all other channels.
* [HW] Use StringAttr instead of StringRef in FieldInfo, nfc
This commit changes to use use StringAttr instead of StringRef
in FieldInfo to avoid unnecessary copies of field names.
Changes are mainly about parser/printer and CAPI.
This commit also changes Struct/UnionTypeImpl to use ArrayRefParameter
instead of ArrayRefOfSelfAllocationParameter in their tablegen
definition. And this deletes unnecessary allocators too.
* [FIRRTL/LowerToHW] Support missing bundle type lowering
This commit makes LowerToHW handle bundle values properly:
(i) bundle registers initialization and (ii) extension of
`getLoweredAndExtendValue` to accept struct/bundle values.
This commit adds an new operation `sv.struct_field_inout` to create
inout memory for hw::StructType. Potentially, this will be used to
modify elements of firrtl bundle types.
This moves the FIRRTL dialect to its own TD file so that it can be
included by the CHIRRTL dialect. This is needed to be able to reference
the FIRRTLTypes.td file from CHIRRTL.td.
CHIRRTL operations will be long gone by the time we get to the
canonicalization pass, so instead of moving these to the CHIRRTL
dialect, just delete them.
When an aggregate FIRRTL type is printed, we elide the `!firrtl` from
the element type. This exposes the functionality so it can be shared
with the new CHIRRTL dialect.
This dialect is going to contain the CHIRRTL operations and types
currently in the FIRRTL dialect. This will provide better structuring
in the MLIR types as we don't want CHIRRTL types to be FIRRTL types.
For more information see this issue here:
https://github.com/llvm/circt/pull/2134
We have one well tested and continuously refined verilog emitter
pass, lets use that instead of duplicating the logic.
This resolves Issue #2282, where it was approved by Martin Erhart.
Adds an innerSym attribute to CompRegOp, which is passed to the RegOp
during lowering. This allows workflows to reliably give a register a
symbol that can refer to the underlying reg.
This commit introduces a new pass `--handshake-add-ids` which will add a unique ID to each operation within a `handshake.func` operation. When present, these IDs are used in both .dot graph printing and FIRRTL instance name generation. Having this provides a deterministic method of tracing back FIRRTL modules to handshake IR or the .dot file.
Add a new pass, RemoveResets, that replaces RegResetOps that have
invalidated initialization values with RegOps. This is part of a series
of patches that are intended to align CIRCT with the Scala FIRRTL
Compiler (SFC) interpretation of invalid. Previously, CIRCT relies on
canonicalization/folding of invalid values to do this optimization.
This pass enables future canonicalization/folding of invalid values to
zero (as the SFC does) without having to worry about performing this
optimization.
Run the RemoveResets pass as part of firtool after ExpandWhens and
before the first canonicalization. This enables conversion of
invalidated RegResetOps to RegOps before canonicalization (eventually)
interprets invalid values as zero.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This change adds an option to ignore the memory read enable signal during
memory lowering to register banks.
According to the FIRRTL spec, the read output is undefined if the read
enable signal is disabled.
But the `firrtl` implementation ignores the read enable signal on latency 0.
This change ensures that, in `HWMemSimImpl` by default the read output is set
to `X` if read enable is disabled, but if `ignore-read-enable-mem` option
is passed, then the read output is set with the data at the read address,
irrespective of the enable signal.
This provides an option to match the Scala FIRRTL compiler behavior.
This extends the FIRRTL fold and canonicalization patterns to treat
`invalidvalue` as a zero if it is an input to a primary operation. This
is inline with what the Scala implementation of the FIRRTL compiler
does.
Doing this removes quite a few of the special cases where certain ops
are aware of `invalidvalue`s and will fold as if it was a zero. The
addition of the `getConstant`, `isConstantZero`, and
`canonicalizePrimOp` helpers allow for most folders and canonicalizers
to not having to bother with `invalidvalue`s, as these helpers
implicitly map `invalidvalue`s to zero constants.
This also subsumes the work done in #2278 and #2198, which selectively
added handling for `invalidvalue`s to the `PadPrimOp`.
The extension of the folders and canonicalizers now makes all the cases
in `invalid-reg-fail.fir` pass, albeit some only after accepting that
the MLIR implementation folds *additional* cases where the Scala one
might just leave an operation untouched. These are marked with a
`<-- fixed; upstream to Scala FIRRTL impl?` and should probably be
upstreamed as additional canonicalizations on the Scala side as well.
This flag appears to be needed to support an upcoming revision of
LLVM. Without this, TableGen complains with:
```
error: defs belonging to more than one dialect. Must select one via
'--(attr|type)defs-dialect'
```
This adds a method to insert ports into an instance op. Since this
increases the number of results of the instance op, it actually has to
be cloned. It is assumed that the user will manually call
`replaceAllUses` and erase the original instance operation. This
functionality is useful for any pass that adds ports to modules.
When an annotation targets only part of the thing it is attached to, it
is represented using a `SubAnnotationAttrs`, which contains the field ID
of its target.
The Annotation wrapper class can be only be created from a
DictionaryAttr. When using a SubAnnotationAttr, it is created from its
internal DictionaryAttr, and the stored field ID is ignored. This makes
it impractical to use `SubAnnotationAttrs` with most of the Annotation
APIs.
This change makes it so the Annotation wrapper holds on to the original
annotation attribute, instead of just a DictionaryAttr. The annotation
wrapper will check which kind of annotation it has internally when calls
are made.
This change then adds a call to `getFieldID`, which return 0 for regular
annotations, and the field id for `SubAnnotations`.
This also changes the equality comparison for two annotations: a
Annotation created from a SubAnnotationAttr will no longer be equal to a
regular annotation when the dictionary attribute is the same.
A very simple pass which removes any buffers present in the circuit. This pass can come in handy if:
1. one would like to re-buffer a circuit
2. one would like to simulate without buffers
3. one would like to simplify the circuit (for visual/.dot inspection)
John Demme