Add option to allow this for compatibility.
Add statistic to count ports added to public modules,
as an interesting bit of information but particularly
to track how many are still being added when updating
a code base to avoid this.
Only warn once per module to keep it from being entirely overwhelming.
(and report how many, in terms of printf's, to convey magnitude)
Split out when-encoding parser behavior to dedicated file,
and look for the deprecation diagnostics in tests that use them.
Currently `DedupGroup` is added to almost every module including `EICG_wrapper`. However EICG_wrapper later becomes intrinsic when a compiler option `fixup-eicg-wrapper` is given. This causes a compilation error since annotation is added to an intrinsic. The right fix is to use to EICG intrinsic in the first place but there are still a few things to migrate ( ExtractInstances). Since dropping DedupGroup annotation on EICG_wrapper is practically safe this PR removes the annotation with a warning.
Fixes a runtime link error on non-capnp builds. Provides an option to
disable ESI cosim. If enabled (the default), produce a CMake error if
capnp is not found.
Constant-like unit-rate operations didn't have any output tokens assigned. Fixed s.t. constant-like operations (with no inputs) are emitted using a `dc.source`.
* [Moore] Add the netOp for net declaration in SV
NetOp is for variable declaration. Net Types defines different types of net connections in SV. There are twelve built-in net types defined
`supply0`, `supply1`, `tri`, `triand`, `trior`, `trireg`, `tri0`, `tri1`, `uwire`, `wire`, `wand`, `wor`, and three special net types:
`interconnect`, `userdefined`, `unknown`. The special ones are marked as unsupported because we have no plan to support them currently.
Corresponding test cases have been added to the parser/print and ImportVerilog pass tests. Add two expected failed netkind test cases -
`interconnect` & `user-defined`.
---------
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
Co-authored-by: Hailong Sun <hailong.sun@terapines.com>
We would previously error if paths are contained in multiply
instantiated modules, because there is no unique path in this
case. However, we could expand out the path into multiple unique paths
in this case, but this is only safe to do if the path is already used
in a list where multiple paths are acceptable.
This relaxes the requirement and implements the path expansion in this
scenario. When we hit a multiply instantiated module, we expand out
all the instance paths to that module from the owning module, and
create multiple annotations and resolved paths.
This exposes a new getAbsolutePaths API where the user may specify an
InstanceGraphNode to use as the top of the returned paths. The
existing API that does not expose this simply calls the new API using
getTopLevelNode(), preserving the previous behavior. An upcoming
change will use the new API to get absolute paths relative to a
different top.
* Fetch reset value from (Fir)RegOp instead of hardcoded signal name
* Add block arg check on reset
* Add test for multiple resets &non-block-arg resets
* Fix test module name
* Add EOF newline to test
* Allow mux selectors to be zero-width or 1-bit (for mux4).
This is legal per FIRRTL spec.
* InferWidths: mux no back-prop.
Fixes https://github.com/llvm/circt/issues/5444
* canonicalizers for small mux selectors
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
Make it easier to extend the set of intrinsic lowering patterns
by implementing the dialect interface for your dialect.
Current lowering patterns are implemented as part of the FIRRTL
implementation of this dialect interface.
This doesn't facilitate adding intrinsic implementations (lowerings)
unrelated to a different dialect but leave that sort of extensibility
as future work.
This implements a new heuristic to determine if a Mux is reachable from a
FirReg. In general an operation is reachable from a register if its in the
fanout of the register. For FirReg lowering, an if/else structure is required
for proper enable inference, if a mux is within the fanout from the register.
The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp.
Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the
reachability. The analysis is built lazily when its queried and the result is
cached to avoid redundant traversal of the IR.
This fixes an issue that caused the merged commit for #6709 to be reverted.
The was to explicitly specify the default size of `SmallVector`.
Port symbols now have no effect on the eventual port name of a module. This also implies that multiple ports can have the same namehint, and will be uniqued when lowering `ibis.container` to `hw.module` (see new test in `containers_to_hw.mlir`).
Move to module pass, and use rewriting framework for safety,
familiariy, and (with some help) simpler lowering code.
Add LowerIntmodules to the pipeline as this is now needed
for compatibility with designs not yet using the new intrinsic format.
The PR implements a new heuristic to determine if a Mux is reachable from a
FirReg. In general an operation is reachable from a register if its in the
fanout of the register. For FirReg lowering, an if/else structure is required
for proper enable inference, if a mux is within the fanout from the register.
The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp.
Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the
reachability. The analysis is built lazily when its queried and the result is
cached to avoid redundant traversal of the IR.
Update the object model generated by the CreateSiFiveMetadata pass to generate
firrtl dialect, instead of om dialect. Ensure all firrtl.class associated with
the metadata are instantiated inside a top level firrtl.class SiFive_Metadata,
which is instantiated inside the top level firrtl.module. This is required for
ensuring that subsequent passes can lower it correctly.
Also generate all the hierarchical paths to the memory and associates them with
the path operation for the memory metadata.
Add parsing and emitter support for FIRRTL intrinsic.
Refactor parameter parsing on (ext/int)modules as these use same syntax.
See tests and PR for more details.
Thanks for the grammar fix, Rob!
Co-authored-by: Robert Young <rwy0717@gmail.com>
Some minor changes to the construction of BitVector attributes in the SMT dialect:
- Fix parsing of smt.bv.constant #smt.bv<-1> : !smt.bv<1> which currently trips the width check due to odsParser.parseInteger creating an unnecessarily wide APInt. The new logic is copy-pasted from the FIRRTL ConstantOp parser. See #6794.
- Change the type of the attribute builder's value argument from unsigned to uint64_t matching the signature of the APInt constructor, to allow values up to 64 bits and avoid architecture dependent behavior.
- Prevent left-shifts wider than (or equal to) the shifted operand's number of bits in the width checking logic to avoid undefined behavior.
FPGAProbeIntrinsicOp is not an expression (not pure and no results!),
mlir::UnrealizedConversionCast is only sometimes expression-like
(and FIRRTLVisitor is for visiting FIRRTL-dialect operations only),
and GenericIntrinsicOp is neither expression nor statement so just
add a special visitor for it.
Update passes using visitors to reflect these changes.
* Revert "[Ibis] Split ContainerOp in two (#6739)"
This reverts commit d17f2f1a1b.
* [Ibis] Introduce 'ibis.design'
Encapsulate everything into a new op. It's an InnerSymbolTable so that
we can identify _everything_ with inner symbols.
Partial progress.
* Hopefully avoid some msvc warnings
* add topLevel attr to containerop
* bug fixes
* Nest createContainerizePass inside of <ibis::DesignOp>
* Work
* Work
* Working
* Self review
---------
Co-authored-by: Blake Pelton <blakep@microsoft.com>
Co-authored-by: Morten Borup Petersen <morten_bp@live.dk>
This commits replaces `--emit-chisel-asserts-as-sva` with an option with more fine grained control.
Specifically an option `--verification-flavor={none, if-else-fatal, immediate, sva}` is added. `none` is the option for the current behaviour that uses per-op configuration (which must be deprecated once after `has_been_reset` is properly used for assertions that are expected to be disabled while pre-resets).
Close https://github.com/llvm/circt/issues/6543
Getting all the ports to lookup one attribute is very expensive. Mainly from GetAllPortLocs requiring several lookups and allocations. Just avoid doing this by not using the summary functions and looking up individual ports directly (as should generally be done to avoid the overly broad expensive functions).
When determining which directory to place a blackbox into, make two
changes to get this working correctly with layers:
1. Never change a directory if one is already specified.
2. Treat any bound instance as not under the DUT.
Taken together, this preserves both the original behavior of grand central
blackbox extraction and causes blackboxes instantiated under layers to be
placed in the testbench directory.
Fixes#6880.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
As we moved companion assume generation to a pass, having `AssertAssume`
would not be necessary anymore. We still need assert instrinsic so
this PR just renames the intrinsic to `assert`
This PR separates UNROnlyAssume generation from AssertOp lowering into a dedicate op.
This commit adds:
* LowerToHW support for `UnclockedPredicateIntrinsicOp` (added in https://github.com/llvm/circt/pull/6867).
* CreateCompanionAssume pass which explicitly introduces companion assumes to the IR. Normal assume and UnclockedPredicateIntrinsicOp are used based on the guard's content.
The commit is intended not to change semantics of generated verilog. This commit should only introduces cosmetic changes regarding guards(because now they are reused).
This adds UnclockedAssumeIntrinsicOp which generates a SV assume statement whose predicate is used in a sensitivity list of the enclosing always block.
* [FIRRTL] Change Port Direction attribute from an APInt to a DenseArray.
APInt requires an allocation to start large values. Using apint for port directions requires copying the apint when inspecting port directions, thus introducing huge amount of copies throughout the code. On large designs this allocation overhead amounted to over 25% of the time spent. DenseArrays are less space efficient (by 8x as used), but can be accessed by reference, removing these allocations.
Add pass that converts instances of intmodules to the generic
intrinsic op (firrtl.int.generic).
Also add optional special-case handling for recognizing extmodule
with defname "EICG_wrapper" as encoding the clock gate intrinsic.
The pass is not included in the pipeline.
Add generic intrinsic operation to FIRRTL. Not used anywhere, just adding to the IR to build on.
Re-use module parameter printing/parsing for use as custom printer on the op.
See PR for more context.
Now that we've added a cached symbol table at the circuit level, we
can use that to look up option groups as well. This didn't have a
major performance improvement on some large designs, but in the
presence of more instance choices, this could help. Regardless, this
is one minor piece to clean up for #6772.
Fix a bug where SVExtractTestCode was not extracting asserts, assumes, and
covers from the verif dialect. This resulted in unexpected end-to-end
"failures" from Chisel where Chisel asserts, assumes, and covers were not
extracted and left in the design.
Fixes#6864.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add support for pre and post increment and decrement expressions, like
`x++` and `--x`, as well as assign expressions, like `a += 5`. Slang
represents these assignments as `Assign(a, Add(LValueRef, 5))` in the
AST. The `LValueRef` node contextually refers to the parent assignment's
left-hand side. To deal with this, also add a corresponding lvalue stack
to the conversion context. Assignments push and pop their lvalues onto
and off of this stack.
These expressions require a mechanism in the IR to express _when_ a
variable is read. To capture this, add a new `moore.read_lvalue` op.
It currently looks like an identity operation with a `MemRead` side
effect. Further down the road, we may want to introduce a proper
reference type for variables, ports, nets, and other things, and have
`read_lvalue` and the various assigns operate on that type instead. This
sets the foundation for that.
Co-authored-by: Hailong Sun <hailong.sun@terapines.com>
Co-authored-by: ShiZuoye <albertethon@163.com>
Co-authored-by: hunterzju <hunter_ht@zju.edu.cn>
Co-authored-by: Anqi Yu <anqi.yu@terapines.com>
Andrew Lenharth