Change FIRRTL's deduplication pass to report all errors arising from
modules marked "must deduplicate" that do not expectedly deduplicate.
This provides a better user experience because they do not have to iterate
on long compiles only to get "one more error".
Fixes#7324.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This PR introduces a new assert property op to the sv dialect and uses that as an intermediary for property assertion emission. This should solve the issue of the polarity being different in SV and in verif for the enable signals ( enable in verif, disable in sv ).
Adds a channel buffer to an ESI channel. Since the channel buffer lowers
to a SystemVerilog primitive, we need to copy the ESI primitives file
into the output dir.
Only affects Questa simulation.
- Fix the build rpath so one can run Questa on the build directory.
- Remove the CXX path as it doesn't seem to be necessary any longer.
- Switch the timescale to something more reasonable.
Casting from interface to operation generates these warnings,
as with other instances resolve by casting from Operation* instead.
> llvm/llvm/include/llvm/Support/Casting.h:490:69: warning: returning reference to local temporary object [-Wreturn-stack-address]
- Older versions of Linux (like the ones we use for Python wheel builds)
need more includes.
- Install backend shared libraries
- Exclude MtiPli from repair
Because the return of 'convertRvalueExpression()' can return '{}'. For example, when we handle the 'x'/'z' value, it will emit an error and return '{}', so we must estimate whether the return of 'convertRvalueExpression()' is '{}'. Otherwise, it will cause a segmentation fault.
This PR removes a canonicalization that incorrectly replaces self-connect registers with their non-constant reset values.
This PR also adds additional conditions for presets. We have to revisit to handle preset values.
Fix#7266.
New pass to verify that channels and bundles are used the appropriate number of times. The wrap/unwrap, pack/unpack operations already have these checks, but when a channel/bundle is produced by a module (or some other op), it is not checked. A pass is the best way I could figure out how to implement the check.
Closes#7286.
Revert version number to 0 to indicate that the JSON schema is not
stable. Also, fix a bug in ROM creation. Bug fix will be tested in a
forthcoming PR.
We can append the appropriate symbol visibility to svmoduleOp according
to the structures of instanceSymbol provided by the slang front-end. slang
provides a function to get the root of the design. Calling this method
could get all top-level instanceSymbols and help determine which ones
should be tagged. Note that the visibility attribute now used does not
contain the `nested`.
This PR basically reverts 4cf7bc9a30 to add a prefix to MemOp instances. Previously we changed to remove prefix since it broke prefixes created in PrefixModules. However https://github.com/llvm/circt/pull/4952 added `prefix` attribute to MemOp so we don't need the workaround anymore. This makes output verilog a lot more LEC friendly. I checked the PR doesn't break prefixes added by PrefixModules on internal designs.
* [FSM]New Builders for StateOp and TransitionOp
1. Create an OutputOp inside a StateOp with the output values instead of an empty OutputOp, which needs to be erased after all.
2. Accept two functions as arguments to create the TransitionOp, which is similar to the creation of sv::IfOp. This would be helpful because one doesn't have to create the blocks and set the insertion point manually, which may cause errors sometime.
This PR removes default implementation of CombDataFlow which indicate an op was sequential. Also implement it for DPI intrinsic.
Close https://github.com/llvm/circt/issues/7229
Since MMIO will be used to transmit things like pointers, we should
probably make it 64-bit data. This seemingly simple change had a bunch
of ripple effects.
The canonicalization for VariableOp is aimed at merging the "easy use" of the variable and its value(continuous assignment) into a new op called assigned_variable. Don't handle blocking_assign and nonBlocking_assign due to the dominance.
The "easy use" is assigning a value to a variable with the whole bit-width, in other words, exclude the bits slice, concatenation operator, etc.
As @youngar explains well, a node was being deleted when it had references. Just route the node through the bounce wire instead of trying to replace it.
Closes#7225
If a backend isn't found in the registry, try to load it dynamically
from some standard places. Note that if one doesn't want to keep the
plugin shared lib in one of those places, one can LD_PRELOAD it.
Linux support only. Windows to come.
Fix https://github.com/llvm/circt/issues/7226. This adds support for specifying input and output names. This uses `;` separated string list following the same design as `guard` parameter of assert intrinsic.
We already had logic to detect if the owning module was in the middle
of a hierarchical path, and build up the prefix just to the owning
module in this case. However, we still used the entire original
hierarchical path in the new path, which caused the prefix to the
owning module to be duplicated. This is fixed by not only setting the
moduleName to the owning module, but also trimming the prefix to the
owning module in the original path.
Since the gRPC server is now going to be used in multiple places AND the RPC server now uses ports 'n' stuff from ESICppRuntime, it is appropriate to move RpcServer into ESICppRuntime proper. This also significantly simplifies the build.
No new code, just movement and CMake changes.
- Rename C++ library to ESICppRuntime.
- Create new ESIRuntime target which builds everything.
- Modify gRPC install to not include libz. (Avoids cmake warnings.)
`impl` isn't being default-initialized on the `RpcServer`, but instead constructed in `RpcServer::run`. Hence, if `RpcServer` is destructed before `run` is called, a nullptr exception may occur.
We've switched from a polling 'pull' method to a callback-based 'push'
mechanism for read ports. Polling (via std::futures) is built on top of
the push mechanism.
The read-ordering problem has also been fixed by using std::futures
exclusively for polling schemes. They also allow for poll-wait-notify
schemes without any changes on our part.
Pybind11 2.10 has a bug related to binding enums. Somehow exposed by a
totally unrelated commit 62cb3d109e.
Upgrading past 2.10 fixed it.
Also fixing some setup.py comments.
After spending a truly obnoxious amount of time fighting capnp and
libkj, we made the decision to switch to another RPC system. We're no
longer modeling and serializing message types in Capnp and we don't need
the performance which capnp/libkj RPC promises, so there's really no
need for the additional complexity. A slower system which is thread safe
should work fine.
This commit breaks the build in a pretty horrible way and is not
intended to be merged on its own. It simply breaks up the diff.
This exposes the ObjectValue Location in the Python bindings using the
C API for MlirLocation. The Location is useful for debugging the
source that created the Object in the first place.
This PR gets rid of the `ltl.disable` op and intrinsic in favor of having an enable operand on the verif assert like ops. This made it trivial to fix an incorrect when condition folding for `AssertProperty`. Most of the PR relates to fixing the chaos that was caused by removing `ltl.disable`.
* Port some of customAssemblyFormat to declarative assembly-format. HW uses unconventional printer so we still need to use a custom directive though.
* Replace manual `get` declarations with TypeBuilderWithInferredContext in several places
* Make banner consistent with others
This pass processes all modules and layers in parallel, and since this
could result in the operation being deleted, could lead to crash when
two side-by-side ops are removed at the same time and try to modify each
other's next and previous pointers. This changes the pass to handle the
part of the specialization which can delete the operation in serial.
This annotation helper is more convenient to use due to being variadic,
and slightly more efficient as it will not create an empty array
attribute if the target has no annotations.
We have a fast path when removing annotations that checks if the
underylying array attr is null, which should be impossible. Remove this
code path and add some asserts.
Common pattern of walk/visit many operations looking for annotations
and removing along the way is taking considerable amount of time
in ArrayAttr::get. It may make sense to rework AnnotationSet to
not promise a non-null ArrayAttr but for now add a fast-path
where it matters -- in removeAnnotations(Operation *op, predicate).
Move the `CombDataFlow` op interface from `FIRRTL` to `HW` dialect.
The op interface is better suited to reside in the `HW` dialect, along with
other interfaces like the `HWModuleLike`.
This makes it more convenient for non-`FIRRTL` dialects to implement ops using
this interface, without introducing a new dependence on the `FIRRTL` dialect,
assuming `HW` dependence already exists.
We can't specialize away layers after they are lowered, so this pass was
placed in the wrong spot in the pipeline. It was a last minute change to
move specialize layers after checking for combinational loops which
caused this bug, as we need to make sure that all diagnostic passes run
before we start deleting logic, otherwise we can hide errors from the
user. This adds a few tests that layer specialization is working as
intended, and that it doesn't prevent detection of errors.
As a part of specializing layers we have to remove any HierPathOps which
included a reference to deleted instances. If any member of the path
array is contained in the deleted references list, we need to delete the
op. There was incorrect use of `continue` which caused us to continue
processing the path instead of skipping to the next path operation,
which could lead to a double free when multiple instances in the path
were removed.
This PR fixes an issue that `emitAsTwoStateType` flag was not propagated for aggregate types.
This PR also fixes a bug that ctypes (int/shortint etc) are used as an inner type of packed types (e.g. `int [2:0]` is invalid) according to SV spec 6.8.
LowerDPI checks that improted DPI functions have the same function
signatures over their call sites. This fixes a bug that mistakenly
regards operand types of call op as input types. Call op has clock and
enable operands so operand types are not equal to input types of
DPI functions.
Previously DPICallLowering called `rewriter.replaceAllUsesWith` for individual
results but it seems that is not equivalent to `replaceOp`.
This also adds missing dialect dependency to seq
Close#7191
This adds `StmtExprVisitor` struct for visitor to handle operations with an optional result. Currently `GenericIntrinsicOp `and `DPICallIntrinsicOp` are added.
Besides that `ExpandWhens` is modified to handle DPI intrinsic.
* Fix paths in tests for windows builds
* Fix patterns that check mlir: backslashes are rendered as double backslashes
* Fix fir emitter for output dirs with backslashes
* Try fixing patterns, again
* FIRLexer: parse escaped backslashes in strings
* Fix more patterns with backslashes
* This time, for an absolute path
This PR introduces a PrepareForFormal pass that tries to alleviate some of the heavy lifting being done in the btor emission. For now this only flattens wires, but in the future in will also handle formal contracts and anything else that is done to make emission for formal tools easier, which is why it's part of the verif dialect and not hw.
This is derived from #7150
* Add getDirectoryAttr helper to HWOutputFileAttr
This helper gets the directory component of an output file name, or returns
nullptr if there is none.
* Output directory control v2
Instead of using an explicit precedence declaration anno to help guide the
assignment of floating modules to output directories, use the directory
hierarchy itself. So if a module is used under directory A/B and A/C, it will
be placed into directory A.
* Support absolute output directories for modules
* Add comment
* Make it so output dir annos only apply to public modules
* Simplify lower layers
* Add ability to configure the output directory of assign-output-dirs
* Update tests
* Address review comments
* Clean up whitespace in test
* clang-format
* Fix up firtool integration test excercising dedup + output dirs
* Address review comments
* [mooretocore] Support namedconstant
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
* Limit type to integertype.
* add mooretocore support
* remove include
* remove verify of hwops
* remove include
* Test added.
* Add test for MooreToCore
* Support any attribute
* Modify test.
* Add symbol for wireOp
* Remove useless include
* Add more test and error cases
* slang-tidy
* some Imporvement
* Improved version
* little change
* Imporve
---------
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
Add a new CombDataflow op interface to FIRRTL.
This interface is used for specifying the combinational dataflow that exists in
the results and operands of an operation. Any operation that doesn't implement
this interface is assumed to have a combinational dependence from each operand
to each result.
Currently only FIRRTL register and memory ops implement this interface, but it
can be used in other dialects that intend to use the CheckCombCycles pass.
This PR modifies ExportVerilog to emit two state types (`bit` in general) for DPI import op. Furthermore, for specific bit width (8, 16, 32 and 64) it emits C-types (byte, shortint, int and longint).
This PR also rejects small integer types other than 8, 16, 32 and 64 bit width since otherwise we have to use`bit` but they are passed by references in DPI. So this PR defines the ABI as "small integers are passed by values, and larger integers are passed by references.
This PR adds DPICallIntrinsicOp and its lowering pass. DPICallIntrinsicOp is lowered into sim.func.dpi.call and sim.func.dpi ops. At FIRRTL level DPICallIntrinsicOp doesn't have symbols and instead LowerDPI pass accumulates call sites and creates symbols for dpi functions. LowerDPI pass directly lowers FIRRTL intrinsic into Sim dialect since FIRRTL doesn't have DPI/Function construct. LowerDPI pass could be simplified (or migrated into LowerToHW) once FIRRTL gets 1st class support for Function. Unrealized conversion cast is used to mix FIRRTL and HW type values before LowerToHW.
ODS InterfacePass generates `canScheduleOn` method with a specified interface in a header file and currently we import every pass declaration through PassesDetail.h. Gcc/clang seem to compile when there is an unknown interface class but MSVC emits an error. So this PR avoids `InterfacePass` in ODS and manually implements `canScheduleOn` in PrepareForEmission.
This PR adds DPI func/call op and SimToSV lowering.
`sim.dpi.func` is a just bridge to `sv.func`. This op can be lowered into `func.func` in the future for Arc integration.
`sim.func.dpi.call` represents SystemVerilog DPI function call. There are two optional operands `clock` and `enable`.
If `clock` is not provided, the callee is invoked when input values are changed. If provided, the dpi function is called at clock's posedge. The result values behave like registers and the DPI function is used as a state transfer function of them. `enable` operand is used to conditionally call the DPI since DPI call could be quite more expensive than native constructs. When `enable` is low, results of unclocked calls are undefined and in SV results they are lowered into `X`. Users are expected to gate result values by another `enable` to model a default value of results. For clocked calls, a low enable means that its register state transfer function is not called. Hence their values will not be modify in that clock.
A function that returns an explicit return is not supported yet.
This commit adds the DUT module instance path to the to the `SiFive_Metadata`
class. This is required to generate the DUT instance path directly from the
OMIR. This will be required to generate DUT relative hierarchy paths for
memories in the seq_mems.json metadata, Since all paths are by default
generated relative to the top level.
This commit creates a list of paths, to handle multiple DUTs even though the
current designs will have a unique DUT.
Bump minimum supported FIRRTL to 2.0.0.
"FIRRTL version" is now required as a result.
Remove parsing of the FIRRTL partial connect operator ("<-"). This has,
for a very long time, been almost unreachable from Chisel-emitted FIRRTL
and is now impossible to emit from Chisel. This has also been completely
removed from the FIRRTL spec in version 2.0.0.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Taps (using probes) support a non-passive source with a passive sink (by their nature), but the hidden option to avoid probes does not.
Detect this specifically and fix by using passive type for wiring from source.
This allows taps of non-ground (non-passive) that work with probes to also work with this option.
* [MooreToCore] Add conversion support for SVModuleOp and InstanceOp
* Trailing newline fix
* Add Fixme
* [MooreToCore] Add a new test case for svmoduleOp and instanceOp
This is a rather crude version without assignOp, variableOp and netOp in the examples.
We generally type-erase objects at the boundary, to avoid needing to
declare the objects' classes as part of the interface. This adds a
cast for the metadataObj reference, so we don't have to declare its
class as part of the interface. The evaluator and any tooling built on
it already know how to "see through" this cast.
... while factoring out `InnerSymbol`+name logic into a new interface that is also used by Ibis port-like ops. This model could probably be factored into the `hw` dialect, seeing as we're also eventually going to divorce symbol names and actual names in `hw.module`.
Also adds de-aliasing logic to `ContainersToHW`, which is required given that `hw.module` doesn't yet split its symbol and name (#7023).
This PR implements ExportVerilog support of sv.func, sv.func.dpi.import, sv.func.call and sv.func.call.procedural.
sv.func emission is similar to hw.module but one difference is a return value. Surprisingly in SV a function name is used as a placeholder for a return value so name legalization properly sets `hw.verilogName` of a returned value to a function name.
Result names of sv.func.call.procedural are attached to temporary registers created in PrepareForEmission. This is similar implementation approach to hw.instance.
[Moore] Modify the tests related to the RefType.
Add a wrapper type(moore::RefType) to work for VariableOp/NetOp, ReadOp, and AssignOpBase, and it can wrap any SystemVerilog types. We added RefType in order to introduce Mem2Reg into moore to eliminate the local temporary variables. Meanwhile, we added a new op named moore.extract_ref which is the copy of moore.extract that explicitly works on the ref type. And moore.concat_ref is the copy of moore.concat. Later, we will tweak union/struct ops like moore.struct_create in order to support the ref type.
moore.variable/moore.net will return a result with ref<T>, it's similar to memref.alloca.
Change moore::ReadLValueOp to moore::ReadOp, it's similar to memref.load. Initially, we need moore.read_lvalue only to service for assigmen operations(like +=, *=, etc). However, moore. read is not only for assignment operations but also to take a value with RefType(ref) and return the current value with the nested type(T). For example, a = b + c, moore.read will take b and c(both are ref<T>), and then return a value with the nested type(T).
We think the MooreLValueType and VariableDeclOp(52a71a6) that had been removed eventually found their proper site.
We also divide convertExpression() into convertLvalueExpression() for the LHS of assignments and convertRvalueExpression() for the RHS of assignments. The former will return a value with RefType like ref<i32>, but the latter returns a value without RefType like i32.
Co-authored-by: Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
This changes pre-passes for ExportVerilog to run on HWEmittableModuleLike instead of HWModuleOp. #6977 is going to add a support for SV func op and legalization needed for SV func as well.
HWEmittableModuleLike is a new interface that inherits Emittable+HWModuleLike. I considered to use a trait but we cannot use a trait for pass scheduling so an interface is used.
Add module types and support for ports to the `moore.module` and
`moore.instance` operations. Also add a `moore.output` operation as a
terminator for modules, similar to the HW dialect. Extend ImportVerilog
to generate ports.
The ports on SVModuleOp follow a similar strategy as in HWModuleOp: all
input, inout, and ref ports are passed to the module as inputs and are
carried inside the module as block arguments, while output ports are
assigned by the OutputOp terminator. The Moore dialect reuses the
`hw::ModuleType` but does not use the `inout` direction. Instead, inout
ports will be represented as inputs with a `net<T>` wrapper type, while
ref ports will be wrapped as `ref<T>`.
Instances work identically to the HW dialect: input, inout, and ref port
connections are carried as operands, while output ports are represented
as results.
This commit also adds module and instance port support to the
ImportVerilog conversion. Regular ports are mapped to corresponding
ports on the module with the appropriate direction. Multi-ports, which
are a weird quirk of SystemVerilog that allow multiple ports to be
grouped up and presented to the outside as a single named port, are
split up into individual module ports. This is necessary since this
group can contain ports of different directions.
Inside a module Slang automatically generates local net or variable
declarations for all ports. The user may specify these declarations
themselves when using non-ANSI port lists, which Slang handles properly.
ImportVerilog inserts appropriate continuous assignments to drive the
actual input port value onto the local net or variable declaration, and
to drive the local declaration's value onto the actual output port of
the module. This properly adapts from SystemVerilog's assignable and
connectable ports that feel like nets or variables, to the Moore
dialect's by-value passing of inputs and outputs.
Instances in Slang have expressions connected to their ports. Input
ports lower this expression and directly use the result as an operand.
Output ports lower this expression and drive it through a continuous
assignment inserted after the instance, with the instance's
corresponding result on the right-hand side of the assignment.
Once we have a `ref<T>` type, and later potentially also a `net<T>`
type, the port lowering shall be revisited to ensure that inout and ref
ports are mapped to net and ref types, respectively. The lowering of
expressions connected to ports requires more care to ensure that they
are appropriately lowered to lvalues or rvalues, as needed by the port
direction. A `moore.short_circuit` operation or similar would help to
connect inout ports to the local net declarations in a module, and to
capture `alias` statements.
---------
Co-authored-by: cepheus <buyun.xu@terapines.com>
Co-authored-by: Hailong Sun <hailong.sun@terapines.com>
We stated in a comment that we copy the leading part of the
hierarchical path from the owning module to the start of the
annotation's NLA. But we never actually did that, so this adds (back)
that logic.
Fixes https://github.com/llvm/circt/issues/7125.
This turns the multiple-instantiation error into a warning in
ResolvePaths and LowerClasses. In real designs coming from Chisel
today, we are not yet able to enforce single instantiation. This was
never a requirement of the original way that we handled hierarchical
paths in EmitOMIR, so this removes the requirement for now. Adding it
back is tracked in https://github.com/llvm/circt/issues/7128.
With this change, the ResolvePaths logic was simplified to stop trying
to disambiguate paths in some cases, and instead allow the annotations
to simply convey the user's requested local or hierarchical path. In
LowerClasses, if there are multiple instances, this means we have
ambiguity. In practice, this logic will produce the same outputs as
EmitOMIR, once we fix https://github.com/llvm/circt/issues/7125.
Add a missing check for absent port location information to
`printModuleSignatureNew`. This would cause crashes if the
`--mlir-print-debuginfo` option was set during emission and there are
not port locations available. This mirrors what we already do for
port attributes.
Thanks @uenoku for pointing this out in #7112.
Create these constants as unsigned of unknown width,
instead of s64.
This way when connecting to the address, we don't emit
a connnect between s64 and something like u3
(requiring casts/trim/etc).
Fix a subtle issue in ImportVerilog's statement converter, where a call
to `convertExpression` returning a null value would not properly be
mapped to a `failure()` result.
The original line was `success(<value>)`, which apparently still returns
success even with a null value. Changing this to `failure(!<value>)`
fixes the issue.
While at it, remove all error test cases that simply check for Slang
frontend errors. These things are already tested in Slang. ImportVerilog
should only test for the errors it generates itself.
* [ImportVerilog]Support union types.
* [ImportVerilog]Rename structMember with structLikeMember
* [ImportVerilog] check the type of new Expressions.
* [ImportVerilog]Add value check for new Expressions.
* clang-format modify recommand
* [importVerilog]Remove useless inlcludes
* [ImportVerilog]Add union size and domain
* [ImportVerilog]Give more specefic errors
This has only been used for probes, but without input probes
this is no longer useful or necessary.
The HW-signal hoisting works well (if limited) and has no
known issues[1] but has yet to be used in practice due
primarily to passthroughs being intentional occasionally
and lacking a mechanism to capture or distill this intent
properly (it must be ""optimized"" yet not).
Since this is unused, and lacking traction on the above,
remove from pipeline and delete this for now instead of
having it bitrot and be a maintenance burden while
adding/completing new features.
Lives on in version control history!
[1] FWIW, see https://github.com/llvm/circt/pull/6115 for
both small example and before/after on chipyard, as well
as testing internally back when this was introduced.
Add the `FindInitialVectors` pass to the Arc dialect which finds
isomorphic operations at the same topological rank and groups them into
`arc.vectorize` ops. This is going to be the starting point for later
canonicalizations and optimization steps to improve the vectors and
apply a cost model.
Move the definitions of packed and unpacked struct types from C++ land
into `MooreTypes.td`. This removes a significant amount of complexity.
With all types moved into the TableGen file, a lot of redundant code can
finally be removed and the parsing/printing can be streamlined
significantly.
This change also drops the `StructKind` enum which was used to discern
structs, unions, and tagged unions, although the ImportVerilog
conversion never generated anything besides structs. Once we add support
for unions in the future, the intention is to define new types in ODS
for the unions and reuse the `StructMember`.
Operations defined through TableGen will use a version of type parsing
and printing that strips away the dialect prefix in case this does not
lead to ambiguities. If an op specifies a type like `UnpackedType`, the
generated parser and printer will call `UnpackedType::parse` and
`UnpackedType::print` in order to parse and print that type. This method
usually prints the type without any dialect prefixes, and often also
without the type name itself (as it is obvious given the type).
Add an implementation for `parse` and `print` to `UnpackedType` which
performs this stripped printing. This makes the assembly more compact
and in-line with what MLIR would generate by default if a
TableGen-specified op would use a TableGen-specified type.
This makes the integer flavor of `IntType` look exactly like the builtin
integer type, which will facilitate a future change from Moore's integer
type to the builtin integer. Parsing is unambiguous, since the stripped
form is only used when the type is clear from the op context.
Move the definitions of all array types from C++ land into
`MooreTypes.td`. This removes a significant amount of redundant code and
simplifies the dialect's type system.
Replace packed and unpacked ranges (`T [4:3]` or `T [2:4]`) with a new
type that discards the directionality and offset of the range. This
information is no longer needed at the IR level. Any meaning that the
offsets have can be encoded in the corresponding ops. Both ranges are
now represented as `array<2 x T>` and `array<3 x T>`, respectively.
Combine unpacked ranges (`T foo [6:2]`) and unpacked arrays
(`T foo [42]`) into a single `uarray<N x T>` type.
* Introduced new ltl ops
* added ops to visitor
* updated exportverilog
* added type inference for intersect
* updated tests
* added fold for trivial case
* Added FIRRTL intrinsics and test
* comments
* updated op requirements
LowerClasses creates an object for a corresponding instance only if the
instantiated module has property ports. But a class can be created for a
corresponding module based on other conditions like, if the module is public,
or instantiates other classes. This results in un-instantiated classes that
donot correspond to the module hierarchy.
This change ensures that if a class is created for a module, the object is also
created from the corresponding instance. Thus the module hierarchy is also
preserved in the om IR. Downstream tools parsing the IR can assume a single
top level class which is required for object model evaluation.
- Recursive source collection
- Run vlog on each file
- Run vlog in a Questa session to improve the speed
- Add no compile option
- Run vopt during compile so missing modules get reported
* [ImportVerilog] Support member-access expression
Support member-access expression.
Add container multiSymbolValue for multi-symbols pointing one value.
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
* [ImportVerilog] Support member-access expression
Separate two containers and their annotations.
* [ImportVerilog] Support member-access expression3
use auto instead of const slang::ast::Expression *
declare concatName with expr.member.name
* [ImportVerilog] Support member-access expression4
Simplfy string allocation.
* [ImportVerilog] Support member-access expression
The signing of unpacked structures is not allowed.- IEEE Standard
* [ImportVerilog] Support member-access expression6
Add packed unsigned struct occasion for testing.
* [ImportVerilog] Support Union Type
Support Union Type
Modify uniont tyep to event type as error type example.
* [ImportVerilog]Add errors example
Add error example for unpacked union.
* [ImportVerilog] Add strucfield op
Define a struct field access op that can represent accesses into struct fields.
* [ImportVerilog] Add struct inject and extract op
Add struct inject and extract op.
Remove union support.
* [ImportVerilog] Support memberaccess
* Removed some useless include.
* fix test error
* Fix errors.sv
* remove space.
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Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
Now that invalid is better defined, we can start propagating it when we can preserver semantics. This means not breaking the one-op-is-one-consistent-value (e.g. not duplicating). The only bit mutating op which is touched by this change is not, which is a pure all-bits inversion, which should be safe (tm).
This converts wires into nodes when there is one write to the wire and it dominates the reads. By converting to nodes, this pass does not have to worry about symbols, references, or annotations. Those are just copied to the node.
This converts wires into nodes when there is one write to the wire and it dominates the reads. By converting to nodes, this pass does not have to worry about symbols, references, or annotations. Those are just copied to the node.
This PR fixes a regression caused by PortAnnotation mutation. We have to batch-update the port annotations to avoid compile time regression. Several other improves are added along with the fix:
* `shouldCreateClass` is slightly expensive since it walks entire IR to check instances. `shouldCreateClass` is already lazily evaluated but however `shouldCreateClass` is immediately called for every module. So this PR changes to compute the all results parallelly beforehand instead of lazy evaluation.
* `std::distance(a, b) == 0` is replaced with `a == b` to avoid potential iterator traversals (maybe it is optimized by clang/gcc though).
* `processPathTrackers` is refactored into a helper struct `PathTracker` so that we can process paths/annotations parallely. We update `pathInfoTable` sequentially afterwards.
* Several operation walks were replaced with instance graph traversal.
It should be NFC completely. Pass should behave exactly the same way.
Using the simulation environment was causing some applications to use
the shared objects distributed with the wheel. That's usually wrong
since the wheel shared objects are compiled with the "old" string C++
library for compatibility reasons. C++ applications which are compiled
against the ESI runtime don't use that.
Fix FoldUnusedPorts to use rewriter for RAUW.
Fix FoldReadWritePorts to use rewriter for RAUW.
Detected by -DMLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
cc #7047.
Fix more RAUW's to use rewriter, inspection.
Retain logic to recognize (but not parse or diagnose) printf's
of the various "flavors" previously supported so that we can reject
designs that rely on this removed support (emit error).
fzi-hielscher