The FullAsyncResetAnnotation is deprecated and replaced by
FullResetAnnotation which includes a resetType argument that must be
'sync' or 'async'. IgnoreFullAsyncResetAnnotation is deprecated and
replaced by ExcludeFromFullResetAnnotation. The new annotations are in
package circt.
The behavior of FullResetAnnotation with resetType == 'async' is
identical to that of the old FullAsyncResetAnnotation. The behavior of
FullResetAnnotation with resetType == 'sync' is very similar, except the
type of the reset wired through will be UInt<1>, and any registers with
an existing reset at all (both sync or async) will be left unchanged
(resetType == 'async' will add async resets to registers with existing
sync resets).
Previously a FIRRTL vector was lowered into a packed array and there was no way
to generate an open array. This PR changes to use unpacked open array which is
supported by several tools (at least verilator and vcs) by default.
Fix https://github.com/llvm/circt/issues/7226. This adds support for specifying input and output names. This uses `;` separated string list following the same design as `guard` parameter of assert intrinsic.
After spending a truly obnoxious amount of time fighting capnp and
libkj, we made the decision to switch to another RPC system. We're no
longer modeling and serializing message types in Capnp and we don't need
the performance which capnp/libkj RPC promises, so there's really no
need for the additional complexity. A slower system which is thread safe
should work fine.
This commit breaks the build in a pretty horrible way and is not
intended to be merged on its own. It simply breaks up the diff.
* Add getDirectoryAttr helper to HWOutputFileAttr
This helper gets the directory component of an output file name, or returns
nullptr if there is none.
* Output directory control v2
Instead of using an explicit precedence declaration anno to help guide the
assignment of floating modules to output directories, use the directory
hierarchy itself. So if a module is used under directory A/B and A/C, it will
be placed into directory A.
* Support absolute output directories for modules
* Add comment
* Make it so output dir annos only apply to public modules
* Simplify lower layers
* Add ability to configure the output directory of assign-output-dirs
* Update tests
* Address review comments
* Clean up whitespace in test
* clang-format
* Fix up firtool integration test excercising dedup + output dirs
* Address review comments
This PR modifies ExportVerilog to emit two state types (`bit` in general) for DPI import op. Furthermore, for specific bit width (8, 16, 32 and 64) it emits C-types (byte, shortint, int and longint).
This PR also rejects small integer types other than 8, 16, 32 and 64 bit width since otherwise we have to use`bit` but they are passed by references in DPI. So this PR defines the ABI as "small integers are passed by values, and larger integers are passed by references.
This PR adds DPICallIntrinsicOp and its lowering pass. DPICallIntrinsicOp is lowered into sim.func.dpi.call and sim.func.dpi ops. At FIRRTL level DPICallIntrinsicOp doesn't have symbols and instead LowerDPI pass accumulates call sites and creates symbols for dpi functions. LowerDPI pass directly lowers FIRRTL intrinsic into Sim dialect since FIRRTL doesn't have DPI/Function construct. LowerDPI pass could be simplified (or migrated into LowerToHW) once FIRRTL gets 1st class support for Function. Unrealized conversion cast is used to mix FIRRTL and HW type values before LowerToHW.
* Added small pass tutorial in getting started docs
* Added small pass tutorial in getting started docs
* Added basic pass tutorial
* Cleaned up pass in getting started doc and added links to better tutorials
* added tutorial pass
* fixed missing imports
* added a test
* added links to tutorial files
* udpated target flags
* nl@eof
* Update GettingStarted.md
* fixed typo in flags
The core type most SystemVerilog expressions are interested in and
operate on is a "simple bit vector type". These are individual integer
atoms like `bit` or `logic`, integral types like `int`, or packed arrays
with a single dimension and an integer atom inner type, like
`bit [42:0]`. So in a nutshell, simple bit vector types are MLIR's `i42`
in the two-valued (`bit`) case, or the four-valued equivalent (`logic`).
Up until this point, the Moore dialect reflected this pattern by
providing and `IntType` for the integer atoms like `bit` and `int`, and
using the `PackedRangeDim` for single dimension vectors of `bit`. A
`SimpleBitVectorType` helper struct would then summarize the _actual_
bit vector that was expressed by the packed range and integer atom. This
makes working with the types in TableGen files very annoying, since the
thing you are actually interested in -- the simple bit vector -- is not
a propery MLIR type, but more like a helper struct on the side.
This commit rips out the existing `IntType` and its composition with a
packed array dimension, and replaces it with a proper simple bit vector
type that is actually an MLIR type. As a result, SystemVerilog types
like `int unsigned`, `bit [42:0]`, `reg`, `logic signed [31:0]`, or
`integer` are all translated into the same MLIR type. This new simple
bit vector MLIR type retains the `IntType` name, and prints as
`!moore.i42` or `!moore.l42`, depending on whether it is a two-valued or
four-valued integer. Single `bit` and `logic` atoms become `i1` and `l1`
respectively.
This makes the Moore type system a lot easier to work with and removes
a lot of unnecessary noise. Operations can now simply use
`llvm::isa<IntType>` to check if a value is a simple bit vector.
We've rejected this during LowerAnnotations since we've had
LowerAnnotations, so it's safe to say this is thoroughly dead.
The internal source of this was removed in January.
In the only supported mechanism for using intrinsics,
the name must be an identifier so just document that.
Periods are nice, we can adjust the FIRRTL grammar / syntax
to allow this in the future if we miss them.
As we moved companion assume generation to a pass, having `AssertAssume`
would not be necessary anymore. We still need assert instrinsic so
this PR just renames the intrinsic to `assert`
This adds UnclockedAssumeIntrinsicOp which generates a SV assume statement whose predicate is used in a sensitivity list of the enclosing always block.
Rename `MIROps.{cpp,h}` to `MooreOps.{cpp,h}`. This makes the dialect be
more inline with others. We can always create additional dialects or
groups of operations later.
Also add the missing `moore` dialect rationale doc and fix the generated
documentation. Non-functional change in terms of operations and types,
but the documentation changes.
This is a preparatory cleanup step for the Slang upstreaming work.
This adds some basic rationale for why it is valuable to be able to
represent computation in the OM dialect, with a couple examples
including arithmetic and container constructions.
Provide intrinsics to capture what today is encoded via printf + when/stop/verif-op pattern matching and XML + JSON parameters.
Compared to assert/assume/cover FIRRTL (textual/in-the-spec) ops, these allow specifying labels that are more than identifiers and have optional compilation guards.
These map to current FIRRTL ops directly, including the various special behaviors that means in practice today (as encoded in LowerToHW):
* Assert implies companion assume emission. Hence `chisel_assert_assume`.
* If the guard `USE_UNR_ONLY_CONSTRAINTS` is present, this companion assume is different, see: https://github.com/llvm/circt/pull/5561 .
There is no "assert" because `firrtl.assert` "concurrent" (SVA) forms always "imply" a "companion assume" and presently there is no FIRRTL dialect encoding for just a concurrent assert without this implied assume.
These are all SVA/concurrent "type".
IfElseFatal:
chisel_ifelsefatal becomes a very specific pattern of verilog that is not concurrent but is modeled that way in the IR (special "assert").
Allow guards and label on the intrinsic but they don't do anything on normal emission flow (`-emit-chisel-asserts-as-sva` will see them however so expose them).
This PR defines a ChainingCyclicProblem, which models a hybrid problem of ChainingProblem and CyclicProblem and adapts the simplex scheduler to solve this problem. It is mainly done by reusing and adapting codes from the two base problems. This problem represents the problem a static HLS tool will solve for loop pipelining.
---------
Co-authored-by: leothaud <dylan.leothaud@irisa.fr>
Add the `dbg.scope` operation to the debug dialect. The op creates an
additional level of hierarchy in the DI, a "scope", which can be used to
group variables and other scopes.
Operations such as `hw.module` introduce an implicit scope. All debug
operations within a module are added to that implicit scope, unless they
have an explicit `scope` operand. Providing an explicit scope can be
used to represent inlined modules.
Scopes in DI do not necessarily have to correspond to levels of a module
hierarchy. They can also be used to model things like control flow
scopes, call stacks, and other source-language concepts.
This commit also introduces an optional `scope` operand on
`dbg.variable`. The `DebugInfo` analysis, which traverses the IR and
builds up a canonical representation of the DI, honors this operand and
adds the variables to the corresponding scope.
John Demme