Fix a few issues in the mem2reg interface implementations of VariableOp,
ReadOp, and BlockingAssignOp. Add tests reduced from the Snitch core
that used to fail before this fix.
Bump LLVM [1] to include an upstream verifier performance fix [2].
This required two minor fixes to CIRCT:
* [HW] Qualify types for safer use in other dialects.
* [ImportVerilog] Fix ternary with diff types, both become Value.
[1]: 5689cccead...c69b8c445a
[2]: 7a98071da2
Fix a bug where the LowerLayers pass could create output ports on a module
lowered from a bind convention layer. Avoid this _almost_ entirely by moving
all subfield, subindex, and subaccess operations (sub-* ops) out of layerblocks
before modules are created (when this is possible).
LowerLayers works by converting "captured" values into ports. However,
the sub-* ops may capture non-passive types allowably, but then never
drive them. E.g., consider the following:
%0 = firrtl.wire : !firrtl.bundle<a : uint<1>, b flip: uint<1>>
firrtl.layerblock @A {
%1 = firrtl.subfield %0[a] : !firrtl.bundle<a : uint<1>, b flip: uint<1>>
%2 = firrtl.node %1 : !firrtl.uint<1>
}
Naively, this "captures" the non-passive %0. However, this is really only
capturing the _passive portion_ of %0 through a subfield. Without this
commit, LowerLayers will try to create a port with the same type as %0
when it should be creating a port with the same type of %1. In order to
determine what the port is, LowerLayers needs to know what is actually
captured and not blindly assume that anything captured needs to be a port.
Because this analysis may be tricky, instead solve this by moving the
sub-* ops outside the layerblock before computing captures. The captures
can then _continue_ to be naively computed by seeing if a value is defined
outside the layerblock.
This approach always works for subfield and subindex. However, this approach
does not work if the subaccess index is defined inside the layerblock. If this
happens, error. This can be revisited later with a complete solution.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Implement the `materializeConstant` function for the Moore dialect and
mark the `ConstantOp` as a `ConstantLike` operation. This now allows us
to write constant folders for various operations. As a first example,
add a constant folder for `ConversionOp` that directly applies domain
conversions (e.g., `i42` to `l42` or vice versa) to constants.
Change the `AssignedVariableOp` to directly return type `T` instead of
the `ref<T>`. This removes the implied allocation and assignment, and
makes this op behave essentially like `hw.wire`.
The canonicalizers for `VariableOp` and `NetOp` can now replace all
reads from the old variable or net with the value of
`AssignedVariableOp` directly, since there is no more `ref<T>` type
involved. This also allows us to fully eliminate unnamed variables and
nets that have a unique continuous assignment.
Also add canonicalizers that remove `AssignedVariableOp` if they shadow
an input or output port of the same name, or if there are multiple such
variables with the same name in a chain.
At a later stage we may want to replace `AssignedVariableOp` entirely
with `dbg.variable`.
Fix issues with verification of subfield, subindex, and subaccess
operations which appear in a layer block. These operations are allowed to
occur in a layer block even if they capture non-passive operands.
This requires reworking layer block verification to no longer check for
operations using non-passive operands. The spec requires that no
operation in a layer block _drives_ a value declared outside the layer
block. However, this is exceedingly difficult to verify due to the fact
that non-passive destinations in ConnectLike operations can be
source-to-destination, destination-to-source, or bi-directional. If the
verifier sees this, just allow it. The FIRRTL pass pipeline will later
canonicalize away flips (i.e., make all types passive) which will then
allow the verifier to check these. This should be revisited in the
future.
Fixes#7451.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Don't check non-passive connects.
The FullAsyncResetAnnotation is deprecated and replaced by
FullResetAnnotation which includes a resetType argument that must be
'sync' or 'async'. IgnoreFullAsyncResetAnnotation is deprecated and
replaced by ExcludeFromFullResetAnnotation. The new annotations are in
package circt.
The behavior of FullResetAnnotation with resetType == 'async' is
identical to that of the old FullAsyncResetAnnotation. The behavior of
FullResetAnnotation with resetType == 'sync' is very similar, except the
type of the reset wired through will be UInt<1>, and any registers with
an existing reset at all (both sync or async) will be left unchanged
(resetType == 'async' will add async resets to registers with existing
sync resets).
The lowering pattern of these two operations crashed when used on aggregate types. This PR adds type conversions for array and struct types and fixes the two lowering patterns by adding support for these types
Change the LowerLayers pass to use the new utility,
`circt::isAncestorOfValueOwner`. This was created from the existing
static function of the same name inside LowerLayers with a streamlined
implementation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add a utility `crict::isAncestorOfValueOwner` that can be used to compute
if an Operation is an ancestor of a Value. This frequently comes up when
trying to compute if a Value is defined _outside_ an Operation with a
region.
The implementation of this is based on @dtzSiFive suggestions.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Extend Moore's `ConstantOp` to use the new `FVIntegerAttr`, which now
allows us to materialize four-valued integer constants in the IR. Also
adjust ImportVerilog to finally properly captured integer literals with
X and Z bits.
With this change, `circt-verilog` is now capable of fully parsing the
Snitch RISC-V core used as a benchmark in the original LLHD paper at
PLDI 2020, and to produce a corresponding blob of IR.
Examples of the extended op:
moore.constant 0 : i32
moore.constant 2 : i2
moore.constant -2 : i2
moore.constant h123456789ABCDEF0 : i64
moore.constant h123456789ABCDEF0XZ : l72
moore.constant b1010 : i8
moore.constant b1010XZ : l8
Sort lines in a CMakeLists.txt file. I'm doing this because I want to add
something to this in a later commit and would like to put it in a sane
place.
h/t @dtzSiFive for the suggestion.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add the `FVIntegerAttr`, an attribute containing an `FVInt` value. This
allows four-valued integer constants to be used as attributes on
operations and for constant folding to occur on such values. In contrast
to the builtin `IntegerAttr`, `FVIntegerAttr` does not have a type yet.
The type can be added later as soon as we have a concrete use case.
I expect us to eventually move `FVIntegerAttr` into the HW dialect once
we are happy with its design. Other parts of CIRCT will eventually want
to reason about four-valued integers as well.
The parsing and printing of the attribute tries to make the `FVInt` read
like a plain old `APInt` when there are no X or Z bits present.
Otherwise it falls back to printing as hexadecimal or binary number.
To distinguish the different representations and to allow constants with
X or Z to be parsed as keywords, a `h` and `b` prefix is used for the
hexadecimal and binary formatting, respectively.
Examples of the attribute:
#moore.fvint<42 : 32>
#moore.fvint<-42 : 32>
#moore.fvint<1234567890123456789012345678901234567890 : 131>
#moore.fvint<hABCDEFXZ0123456789 : 72>
#moore.fvint<b1010XZ01 : 8>
- Got an integration test which wasn't running working.
- Fixed a pybind11_stubgen error.
- Fixed an AppID constructor warning.
- Mitigated a poor hash function.
Add a poll method to ports, a master poll method to the Accelerator, and the ability to poll from the service thread. Also, only spin up the service thread if it's requested.
The service thread polling (in particular) required some ownership changes: Accelerator objects now belong to the AcceleratorConnection so that the ports aren't destructed before the service thread gets shutdown (which causes an invalid memory access). This particular binding isn't ideal, is brittle, and will be an issue for anything doing the polling. Resolving #7457 should mitigate this issue.
Backends are now _required_ to call `disconnect` in their destructor.
Add more utilities to help with resizing `FVInt`s, including
- counting the active bits for signed and unsigned interpretation
- truncation
- zero/sign extension
Also add a default constructor that produces a zero-bit zero value,
allow `FVInt`s to be hashed, and consider bit width for equality
comparisons.
Printing of `FVInt`s would continuously shift the value right by the
log2 of the radix. This triggers an assertion in `APInt` in the case
where the bit width is less than the number of bits being shifted.
Precompute a symbol to layer mapping inside LowerLayers and uses this
instead of a symbol table. This is both faster and avoids problems of
trying to compute a symbol table while modules may be created.
Repurpose the functions that were being used to create macro declarations
to also compute this symbol to layer mapping. Rename these to indicate
that they are now doing generic layer preprocessing.
Fixes#7434.
h/t @youngar for the fix suggestion.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Practically it is very useful to verify equivalence between modules in two different MLIR files. This commit changes `inputFilename` to a list and implements a very simple module merge that moves operations in the second module to the first by resolving the symbol.
This PR adds an option `--shared-libs` to load shared lib in the JIT engine in a similar way to what circt-lec does for loading z3 shared lib. With this change DPI library could be linked in arcilator.
This PR implements initial support for lowering Sim DPI operations to Arc.
* sim::LowerDPIFuncPass implements lowering from `sim.dpi.func` to `func.func` that respects C-level ABI.
* arc::LowerStatePass is modified to allocate states and call functions for `sim.dpi.call` op.
Currently unclocked call is not supported yet.
The ibis.design op will be removed after the IbisContainersToHW pass, and there may be ibis.component's inside the design that have the same name as the design; we want that name to persist, and not be falsely considered a duplicate.
Co-authored-by: Morten Borup Petersen <mpetersen@microsoft.com>
Martin Erhart