An ESI system manifest is intended to describe the parts of a particular
accelerator which may be relevant to software. It will eventually
replace the services metadata json.
This first PR only outputs types on cosim ports.
Adds a new operation to the MSFT dialect which specifies a multicycle path constraint in between two symbols.
This implementation does not opt in to the whole dynamic instance hierarchy specification of MSFT; do we want to do that? Would have to require some thinking about what it means that a PD constraint refrences two dynamic instances, wherein `msft.instance.dynamic` currently expects all nested pd constraints to reference the parent instance exclusively.
To this, i don't think it will be needed in our immediate usecase, anyways (assuming we're going to use `hw.path.to_this` which itself will generate the `hw.hierpath` and _not_ use the dynamic instance hierarchy support in MSFT).
Also splits `DynInstDataOpInterface` into a two interfaces; one base interface (anything that pertains to dynamic instance data) and the `UnaryDynInstDataOpInterface` which refers to all data ops which access a single location - some additional boilerplate is introduced since the current implementation of OpInterface's doesn't seem to support inheriting interfaces implementing parent interfaces (everything is expected to be defined by the implementing op).
Exported TCL example:
```tcl
proc reg_0_multicycle_config { parent } {
set_multicycle_path -hold 1 -setup 2 -from [get_registers {$parent|reg_0}] -to [get_registers {$parent|reg2}]
}
```
Treat blockargs like other values and let the asm name hint interface compute names for them. If the port name is a legal ssa name, it will be used, otherwise the legalization will compute a new name based on the port name. This has stable round-tripping after the first round, which is consistent with other ops which provide ssa name hints.
RecursiveMemoryEffects and RecursivelySpeculatable traits provides automatic derivation of side-effects of operations but these effects are computed by recursive IR walk. This is problematic for firrtl.when since when operations are often deeply nested, which prevents us from running canonicalizers before ExpandWhens. This PR just removes these traits and add canonicalizers for whens manually.
firrtl.instance with lowerToBind is lowered into bound instance and symbols are created for the instances. There was a bug that symbols were generated by instance names, not by an appropriate helper so there could have been name collisions. This commit fixes the issue by using inner symbol generation helper.
This also fixes symbol creation for empty port names as well.
This commit adds strip option to drop name pass. Even though there is none option but none option does keep existing names. strip explicitly strips all names to remove variable names form Chisel.
Previously Namespace::newName could return empty string for empty string.
This is a problematic behaivor since primary use cases of Namespace is
symbol generation but empty string cannot be used a symbol.
For example HWExportModuleHierarchy crashed with an instance with an
empty name.
This commit fixes the issue by pre-registering empty string in a constructor of
Namespace.
This PR does an overhaul of how path related operations work in the OM dialect.
When OM classes are created from FIRRTL, a base path is now fed through the
class hieararchy. All paths to hardware objects are now created relative to
the base path. The `path` op has been renamed to `path_create`, and now takes
a basepath SSA parameter, which means that it is impossible to create a path
which is not relative to some base.
A second set of operations to create "frozen paths" have been added. In
FreezePaths, we lower all path operations to hard-coded strings, which allows
us to remove the hardware from the OM IR and still be valid. These operations
have been changed to return `FrozenPathType`, which is to make sure that people
don't try to inter-mix the two kinds of path types. The intention is that the
evaluator will only understand frozen paths.
The PathAttr in OM no longer represents the entire target path, but just the
list of instances which lead up to it.
This also adds an OM utility for parsing FIRRTL style target strings, which is
used in the `frozenpath_create` MLIR assembly format. The existing APIs
contained in FIRRTL were not suitable since these new strings do not include
the circuit name, and we need some restrictions for parsing base paths, which
can not target components. The new parser is a bit more resilient to badly
formed path strings. In the future it may be possible to reunite these two
bodies of code.
The existing python support for paths had to be removed.
The default `install` command doesn't install LLVM utils Filecheck/not/count. Downstream users of CIRCT might want to use FileCheck directly so this PR adds `-DLLVM_INSTALL_UTILS=On` to cmake options. It increase 1MB of release artifacts (85MB->86MB) so I believe that's ok.
Tested by https://github.com/llvm/circt/actions/runs/6483396914.
Instead of the `--instantiate-companion-only` flag, Grand Central now takes a `--companion-mode` flag which specifies the handling of companion objects. The modes are:
* `bind`, the original behaviour
* `instantiate`, which creates explicit instances
* `drop` which removes companions and companion-only sub-hierarchies from the design
This PR ads MLIR pass plugin functionality to firtool pipeline to dynamically load pass plugins and execute passes.
`*.so` file is load with`--load-pass-plugin` option. Currently we can insert passes to 4 places in the pipeline: (1) after FIRRTL parsing (2) before LowerToHW (3) after HW lowering (4) after SV lowering.
In doing so, also opt to move to a keyword style assembly format, rather than a flat list of operands. This is needed to resolve the now three different, optional, operands that can occur in the assembly format (reset operands, clock-enable, and the power-on operand).
To avoid making things too complicated, a keyword is required for either group, e.g.
> `seq.compreg %in %clk reset %rst, %rstValue ce %ce powerOn %po`
+ some related cleanups in places where the default generated builder was being used (without good reason).
Keep FIRRTL-only for now due to dependence on dialect-specific
mechanism to get port number from block argument.
(HW has this but don't want FModuleLike dep in HW)
Keep forceable for now-- it's needed for uninferred resets presently,
and has slightly better (if not ideal) behavior when attempting
to rwprobe a non-passive aggregate.
Accordingly the spec test `force_nonpassive.fir` now fails.
We can't rwprobe() an aggregate that /must/ be lowered. Forceable
tries to allow this, but when using symbols this is just rejected.
Force of non-passive will soon be unsupported and spec updated to make illegal.
These disappear early but some diagnostics, such as flow checking,
use this method so implement it.
This shouldn't be "unreachable", but that's a different fix.
Having an `sv.xmr.ref` op inside a procedural block such as
`sv.alwayscomb` triggers an assertion in `PrepareForEmission`. The pass
would identify the ref op as having side-effects and then go ahead and
try to pull it outside the procedural block. Doing so would create a
`sv.reg` op with multiple nested inout types, which breaks.
Fix the issue by marking the `sv.xmr.ref` op as pure. Taking a reference
to something does not have a side-effect. It's accessing what's behind
the reference that has side-effects.
This commit adds support for graph regions for evaluator.
`ReferenceValue`, a new subclass of `EvaluatorValue`, is added to behave as pointers. `ReferenceValue` can be used as alias to different values and is created for `class.object.field` operation because `class.object.field` can access fields across class hierarchies and the fields might not be initilized yet. `RefenceValue` is not exposed to outside of evaluator implemenation. `EvaluatorValue::finalize` shrinks intermidiate `RefenceValue` in the evaluator value.
Evaluation algorithm is changed to worklist-based iteration. `instantiae` method first traverses the whole IR including sub-class, and create partially evaluaed values for all values and add these values to the worklist. After that we evaluate values until there is no partially evaluaed value.
Fix https://github.com/llvm/circt/issues/5834
This adds more path types which will be used for greater safety in OMIR. This
change splits regular paths in to BasePathType and PathType, where the
BasePathType is only capable of representing paths through the instance
hierarchy, without being able to target hardware components such as wires and
registers. In the future, all paths can only be created relative to some base
path. This also adds a FrozenBasePathType and FrozenPathType, which will be
used to represent lowered paths which no longer depend on the hardware hiearchy
being present in the IR.
CIRCT will eventually want to be able to emit debugging information
alongside its Verilog and other outputs. This commit adds a basic
`DebugInfo` analysis that traverses the IR, collects information in
whichever format we chose to annotate it in the IR, and forms a separate
graph of DI nodes that can be inspected easily.
The rationale behind a separate DI graph is to decouple debug info
formats from in-IR storage. For example, we may want to emit the DI into
a JSON file (which is what the experimental HGLDD does), or dump the DI
in a human-readable form for testing. In the IR, it is not yet clear if
we respresent DI as separate ops, attributes on existing ops, and how
attributes express the DI graph. For example, do modules list their
variables, which makes removal hard, or do variables point to their
parent modules? The `DebugInfo` analysis abstracts over this IR encoding
matter and presents the DI in a format that is easily emitted. (Modules
list their contained variables.)
This commit also adds a `DebugInfo` MLIR translation library to CIRCT.
It implements DI emission as straightforward translations, allowing for
DI to be emitted as:
- `circt-translate --dump-di` for human-readable testing; and
- `circt-translate --emit-hgldd` and
`circt-translate --emit-split-hgldd` for an experimental JSON format
When compiling a design with firtool, the `--emit-hgldd` option can be
used to generate `*.dd` companion files alongside its SV output. This
relies on Verilog emission locations to be annotated in the IR, which
is done separately in PR #6092.
The current logic doesn't support freezing paths with multiple public
modules. In the current setup, multiple public modules are allowed, so
this updates the instance graph traversal to allow rooting paths at
the nearest public module.
John Demme