Coalesce SystemVerilog's `shortreal`, `real`, and `realtime` types into
a single `!moore.real` type understood to be 64 bits wide, and move the
definition from C++ land into `MooreTypes.td`. Once ImportVerilog
actually supports expressions on real values we may want to revisit this
type and either replace it with the standard `f32` and `f64` types, or
create dedicated types for `shortreal`, `real`, and `realtime`.
* [FIRRTL] Fixup FileCheck directive in convention.fir.
Caught by filecheck_lint.py
* [Scheduling][NFC] Alter check prefix to avoid false-positive lint.
As-is, "2:" is reported as possible typo for "LP:".
Use slightly longer prefix to get lint check to pass.
* [Ibis][NFC] Alter mechanism used to disable check directives.
Use "COM:" to prefix lines that we want to ignore,
which ensures filecheck_lint.py understands this as not a mistake.
This PR adds an op `sv.func.dpi.import` for "emitting" DPI import statement. `sv.func.dpi.import` doesn't declare function but it takes a function symbol to emit import statement. This design is similar to what `sv.macro.ref/def` does and it enables us to decouple function declaration and emission.
```
// CHECK-LABEL: import "DPI-C" linkage_name = function void function_declare1(
// CHECK-NEXT: input [1:0] in_0,
// CHECK-NEXT: out_0,
// CHECK-NEXT: in_1,
// CHECK-NEXT: output out_1
// CHECK-NEXT: );
sv.func.dpi.import linkage "linkage_name" @function_declare1
```
This PR adds function call constructs (sv.func, sv.return and sv.func.call) to SV dialect.
* `sv.func` -- this op is between hw.module and func.func. This op implement interfaces `PortList`, `HWModuleLike` and `FunctionOpInterface`. Similar to hw.module, we can preserve argument names and mix the order of input and output arguments. Following func.func empty body indicates that the op is a declaration. Currently sv/func is defined as "automatic" function in SV.
* `sv.return` -- terminator for sv.func. We cannot reuse neither hw.output nor func.func since they have constraints on parent op(and I think it's not reasonable to loose them).
* `sv.func.call` and `sv.func.call.procedural`. Two operations are added because output arguments cannot be used non-procedural regions.
Move generic functionality into Capnp library. This divorces it from the
DPI server, allowing other things to use it. Additionally, divorce
server from general functionality to make adding a client thread easier.
If the new op's result doesn't match, insert a wire + connect
(if valid) to handle the mismatch.
For intrinsics that lower to ops with return type inference,
the inferred type may be different than the declared type
(e.g., `UInt` vs `UInt<1>`).
This adapts the conversion pass to match the recently agreed upon definition for division by zero. Integration tests for circt-lec are added to check the behavior. Note that two syntactically equivalent modules are not considered equivalent if they aren't guaranteed to deterministically produce the same outputs. Alternatively, we could consider two undefined output values equivalent by modeling each value as a pair of a boolean and the bit-vector where the boolean determines if the value is undefined, then two outputs are equivalent if either the boolean is true or the boolean is false and the bitvectors match. There are probably use-cases for both, so maybe we'd want a flag to let the user decide.
Since nlohmann_json is a pretty common dependency, if that target already exists, don't re-download it and run its CMakeLists. This is helpful when the ESI runtime is being itself fetched through cmake `FetchContent`.
Introduce an op to specific a list of names which Export Verilog should never use anywhere. Applies to module names, port names, reg/wire/logic names, etc.
Verification for OM object fields performs global analysis on a symbol table op. This cannot be done efficiently today within symbol table verification without nested symbol tables. So this PR separates the verifier into a dedicated pass and run the verification at several times in the pipeline.
There is no good way to use the binaries included with the wheel.
Essentially, they are built with the old `std::basic_string` but modern
software uses `std::__cxx11::basic_string`. There is now way to change
this behavior (AFAICT) in manylinux2014. Newer manylinux images have a
way, but we need compatiblity back to glibc 2.17, which none of them
provide.
* Added small pass tutorial in getting started docs
* Added small pass tutorial in getting started docs
* Added basic pass tutorial
* Cleaned up pass in getting started doc and added links to better tutorials
* added tutorial pass
* fixed missing imports
* added a test
* added links to tutorial files
* udpated target flags
* nl@eof
* Update GettingStarted.md
* fixed typo in flags
The annotation `AddSeqMemPortsFileAnnotation` causes the pass
`AddSeqMemPort` to add verbatim ops for the SRAM metadata file.
The file lists each SRAM and provides the mapping to
where it is in the hierarchy, and gives its IO prefix at the DUT top level.
This PR updates the pass to use `HierPathOp` to print the SRAM instance path,
instead of the raw list of symbol references.
This is required to ensure that the instance path is valid, even if the hierarchy
is updated by following passes.
This fixes a `firtool` crash that is exposed when using `AddSeqMem` along with
`ExtractSeqMem`. Which is due to invalid symbol references in the `varbatim`, after
the hierarchy was updated. Even though, this particular use case is invalid, as these
two SRAM annotations cannot be used together, it can still be triggered by other
transformations.
Note: This metadata will soon be moved to OM, in a followup PR.
The core type most SystemVerilog expressions are interested in and
operate on is a "simple bit vector type". These are individual integer
atoms like `bit` or `logic`, integral types like `int`, or packed arrays
with a single dimension and an integer atom inner type, like
`bit [42:0]`. So in a nutshell, simple bit vector types are MLIR's `i42`
in the two-valued (`bit`) case, or the four-valued equivalent (`logic`).
Up until this point, the Moore dialect reflected this pattern by
providing and `IntType` for the integer atoms like `bit` and `int`, and
using the `PackedRangeDim` for single dimension vectors of `bit`. A
`SimpleBitVectorType` helper struct would then summarize the _actual_
bit vector that was expressed by the packed range and integer atom. This
makes working with the types in TableGen files very annoying, since the
thing you are actually interested in -- the simple bit vector -- is not
a propery MLIR type, but more like a helper struct on the side.
This commit rips out the existing `IntType` and its composition with a
packed array dimension, and replaces it with a proper simple bit vector
type that is actually an MLIR type. As a result, SystemVerilog types
like `int unsigned`, `bit [42:0]`, `reg`, `logic signed [31:0]`, or
`integer` are all translated into the same MLIR type. This new simple
bit vector MLIR type retains the `IntType` name, and prints as
`!moore.i42` or `!moore.l42`, depending on whether it is a two-valued or
four-valued integer. Single `bit` and `logic` atoms become `i1` and `l1`
respectively.
This makes the Moore type system a lot easier to work with and removes
a lot of unnecessary noise. Operations can now simply use
`llvm::isa<IntType>` to check if a value is a simple bit vector.
Add a `circt-capi` target that depends on all C API libraries. Introduce
a new `add_circt_public_c_api_library` CMake function that wraps around
the MLIR equivalent, but also adds a dependency from `circt-capi`. Make
at least the short integration tests CI job build the `circt-capi`
target to ensure it has a bit of CI coverage.
Disallow input probes.
cc chipsalliance/firrtl-spec#183 .
Adds verifier for this, and mostly updates tests.
Delete ProbeDCE.
Many passes can (and should) be simplified as they do not need to consider this any longer.
* llvm-bump
* llvm-bump (again)
* [FIRRTL] AnnoTarget: use LLVM style casts (#7007)
This changes AnnoTargets to use LLVM style casts instead of "trailing"
member functions. The LLVM style casts are now usable with AnnoTargets
with improvements to the upstream framework. The current style of cast
used with AnnoTargets will no longer be supported by TypeSwitch, so this
PR switches to the recommended idiom.
Authored-by: Andrew Young <youngar17@gmail.com>
* updated cast uses
This changes AnnoTargets to use LLVM style casts instead of "trailing"
member functions. The LLVM style casts are now usable with AnnoTargets
with improvements to the upstream framework. The current style of cast
used with AnnoTargets will no longer be supported by TypeSwitch, so this
change is needed to bump LLVM.
Instead of annotating types as signed or unsigned, make Moore dialect
types signless and move the signedness into operations. This affects
division, modulus/remainder, and comparison operations. These now come
in a signed and unsigned flavor. ImportVerilog consults the Slang AST
type to determine signedness when creating Moore dialect ops. The Moore
types themselves now no longer carry any sign information. This
significantly simplifies the dialect and takes the type system one step
closer towards having just a basic two- and four-valued bit vector type.
Remove the `format` functions from the types in the Moore dialect. These
could format a type as SystemVerilog syntax to a certain extent, but
they are unused in practice. The formatting was useful in the original
Rust implementation to produce nice error messages during type checking.
Since Slang performs type checking for us, the formatting is no longer
needed.
They are not limited to appearing on module ports.
Compute presence of full-async-reset accordingly,
and be sure to remove those annotations as well.
Fix various amounts of non-functional / vacuously passing tests.
Add the google-global-names-in-headers rule to the list of clang-tidy checks to prevent namespace pollution.
This is intended to flag global using-directives in header files during PR checks. Collisions between the llvm and the mlir namespace have caused obscure build failures on Windows in the past. #6844 should have removed all existing occurrences in the CIRCT code base.
These are not understood in a non-local way, reject them.
Docs say this annotation cannot be used on a module instantiated
multiple times (apparently) so non-local should never be needed.