Commit Graph

3356 Commits

Author SHA1 Message Date
Hideto Ueno 6be754b850
[ExportVerilog] Make `hoistNonSideEffectExpr` hoist inout chains (#2405)
This commit fixes the crash of disallowLocalVars mode for the IR with
array_index_inout/struct_field_inout and sv.read_inout.

Currently `hoistNonSideEffectExpr` doesn't hoist array_index_inout
and struct_field_inout because they are considered to be lvalues.
This is true only if they are not read. They might become rvalues
afterwards so we have to hoist them as well as read_inout op.
2022-01-10 06:50:54 +09:00
Morten Borup Petersen 31d5b4864b [HandshakeToFIRRTL] Support none-typed muxes 2022-01-08 18:48:25 +01:00
John Demme 1c13db6c9c [MSFT] Cleanup partitioning pass code
- More names for better debug.
- Clean some code.
2022-01-08 03:28:08 +00:00
Andrew Young 319535af03
[Reducer][FIRRTL] Fix memory stubber for memories with bundles (#2383)
This adds some additional casting and proper connections to the memory
puts in the face of bundle types.
2022-01-07 19:30:24 -05:00
Schuyler Eldridge bbc9cbebc1
[LowerToHW] Support ForceNameAnnotation instances (#2432)
Add handling of Chisel's "forceName" API during FIRRTL Dialect to HW
Dialect conversion.  This can be used to guarantee that an instance has
a specific name.  The full Chisel API can be used to also force the
names of signals, but this is not supported.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-01-07 19:27:49 -05:00
Andrew Young 27066d7e9c
[FIRRTL] Clean up and fix assertion parser test case
After merging the implicit CSE for subfield operations, the output of
this test case broke.  The easiest way to fix this was to stop using a
bundle, which was not important for the test.
2022-01-07 14:40:43 -05:00
Andrew Young 5723b66622
[FIRRTL] Add a subaccess cache to the fir parser (#2364)
This adds an implicit CSE for subindexes and
subaccess to the FIRRTL parser.  Due to the nature of the FIRRTL textual
format, we create an incredible number of these things which slows down
the initial IR generation.  On my laptop this sped up a test case from
13-15 second to 8-9 seconds.
2022-01-07 14:08:36 -05:00
Schuyler Eldridge 5096dc6d10
[FIRRTL] Add ParamDeclAttr, use for FExtModule (#2411)
Add HW Dialect's ParamDeclAttr to the FIRRTL Dialect.  This commit only
adds this attribute, but does not use it.  This commit is part of a
series of commits that migrate FIRRTL external modules to use HW-like
parameters.

Change FIRRTL's ExtModule to use ParamDeclAttr for parameter storage as
opposed to using a dictionary.  Modify parsing/printing to put
parameters in a carat-delimited area before ports (just like how HW
Dialect does this).

This makes NO modifications to the way ExtModule is represented.
Parameter values are still stored on the ExtModule and not on the
instantiation.  This will be changed in a later commit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-01-07 13:30:38 -05:00
Morten Borup Petersen 8e4467132c
[Handshake] Allow simple merges in canonical form (#2430)
In trying to get function pipelining to work, it finally seems like we've found the issue for why this hasn't been working. If we keep simple merges, and then add buffers to their outputs, function pipelining looks to be working.
This commit allows simple merges in canonical handshake IR, but keeps the option of removing them through a separate pass. After buffer insertion, the merges will be redundant, but we must keep them (at least for now) to guide buffer insertion.
2022-01-07 18:59:22 +01:00
Morten Borup Petersen 7406aadb1b
[Handshake] Canonicalize away sunk buffers (#2431) 2022-01-07 17:14:06 +01:00
Prithayan Barua cab3bf93c0
[FIRRTL] Replace DontTouch annotation with symbols (#2407)
This change removes the usage of DontTouch annotation from FIRRTL dialect,
 and replaces it with `inner_sym`.
Currently, symbols and the annotation, both block any canonicalization/constant
 propagation through them. Replacing the check for DontTouch annotation with
 the `inner_sym` will simplify the implementation. 

Changes in this PR:
1. Remove the `DontTouch` annotation while parsing and instead add a symbol
 to the op.
2. The DontTouch annotation can remain after parsing if it only applies
 to a subfield.
3. Add `inner_sym` to `CHIRRTL::SeqMemOp` and `CHIRRTL::CombMemOp`, and
 propagate the symbol to `FIRRTL::MemOp`
4. During `LowerTypes`, add the appropriate symbols if `DontTouch`
 subfield-annotation present.
5. Remove the check for `DontTouch` annotation from `Annotations` and
 canonicalization. Instead only check for symbols.
6. `LowerTypes` will silently drop symbols on aggregate types while lowering.
 Remove the errors.

Followup cleanup work pending after this commit:
1. All clients for `inner_sym` must verify the appropriate symbol exists.
2. Remove usage of `DontTouch` annotation, that is no longer required.
2022-01-07 07:53:03 -08:00
John Demme 1594727822
[MSFT] Fix naming issue in `MSFTModuleOp::removePorts` (#2427)
We were fixing up the function type, but neglected to fix the `argNames`
and `resultNames` attributes. This did not affect functional
correctness, "just" the port names.
2022-01-06 15:52:00 -08:00
Morten Borup Petersen 5d1a33ef81
[Handshake] Add new `select` operation (#2423)
The select operation will select between two inputs based on an input conditional. The select operation differs from a mux in that:
1. both operands must be valid before the operation can transact
2. both operands will be transacted once one of them is selected

We previously lowered select operations directly to mux'es, however, this is incorrect. Since a mux will only transact the selected input, the other input (and the entire upstream path that generates the input) will be left stuck, waiting for the mux to transact.
2022-01-06 18:27:23 +01:00
Andrew Lenharth c190f6f94d
[FIRRTL] Value probe operation (#2425)
A minimal semantics value probe operation which allows extracting values out of a module without needing to route each through a symboled entity which restricts transformation.

This will be used for binds and GrandCentral views.
2022-01-06 10:17:14 -06:00
Morten Borup Petersen 898118be38
[StandardToHandshake] Optionally connect constants to Source ops (#2422)
Control-network connected constants may help debugability, but may result in slightly larger circuits. This commit provides an option to connect constants to Source ops instead.
2022-01-06 17:00:29 +01:00
mikeurbach c9c50d2889
[MSFT] Add optional sub-path to PhysLocationAttr. (#2421)
Previously, a sub-path could be specified by encoding it in the name
of the attribute using a certain scheme. This is brittle and
non-standard. To make this more natural and robust, the sub-path is
added as a field of the attribute definition as a StringRef. It is not
required, in which case an empty StringRef can be used. The attribute
name for placement attributes is no longer used in any logic.
2022-01-05 18:39:54 -07:00
Morten Borup Petersen 811fa5fd28
[Handshake] Always add buffers to unbuffered channels in bufferAllStrategy (#2418)
Due to the previous implementation of this function being based on a graph traversal which stopped at buffer ops, running bufferAllStrategy did not actually "buffer all" unbuffered channels, if some buffers already existed.

This commit simplifies bufferAllStrategy to do what is promised.
2022-01-05 13:46:28 +01:00
Morten Borup Petersen dfbafcb6ba [Handshake][NFC] Rename HandshakeDataflow to StandardToHandshake 2022-01-05 09:03:56 +01:00
Morten Borup Petersen 01469f03f6 [Handshake][NFC] Rename HandshakeDataflow to StandardToHandshake 2022-01-05 09:02:01 +01:00
Morten Borup Petersen 3044c4efdd
[HandshakeToFIRRTL] Check single-use precondition before lowering (#2417)
Partially reverts 1d55044, and now only checks the precondition instead of running the fork/sink materialization pass.
2022-01-05 08:18:36 +01:00
John Demme 91e7297d5e [FIRRTL] Fix Questa lint integration test 2022-01-04 17:38:40 -08:00
John Demme bd3a6499f7
[MSFT] Wire cleanup pass (#2410)
Another step towards #2365. This pass 'bubbles up' wires which are merely pass throughs in a given module. It then 'sinks down' wires which are looped back in the instantiation. Together with the entity movement piece, this effectively moves the wires as well. Does not handle wire manipulation operations, which also need to be moved/copied.
2022-01-04 15:12:43 -08:00
Morten Borup Petersen 4fc4a870fd [Handshake] Fix roundtripping of source op 2022-01-04 11:31:50 +01:00
John Demme 922282ca83
[MSFT] [NFC] Refactor design partition pass to share code (#2416)
Enable code sharing with the future wire cleanup pass. Move utility methods into new super class. Create a "framework" method for updating instances.
2022-01-03 16:18:40 -08:00
John Demme 117262aa68
[MSFT] Use MSFTModuleOp for design partitions (#2415)
The design partitioning pass used to build HWModuleOps. The new wire
cleanup passes, however, will be operating on the design partitions so
the modifying extensions will come in handy.
2022-01-03 16:14:30 -08:00
Morten Borup Petersen 675b7da6f6
[HandshakeToFIRRTL] Ensure materialized IR before conversion (#2412) 2022-01-02 18:42:12 +01:00
Hideto Ueno d80618a17e
[SV] Allow verbatim to have non-integer type (#2408)
In aggregate preservation mode, GrandCentral may create VerbatimExpr ops
with aggregate types. This commit allows verbatim to have non-integer types 
such as a struct type or array type.
2022-01-02 12:40:16 +09:00
Hideto Ueno 41a6b2b89d [HW] Use llvm::all_of in hw::isHWValueType, nfc 2021-12-31 23:03:23 +09:00
Schuyler Eldridge 91f308a32b
[FIRRTL] Whitespace cleanup, NFC
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-12-31 00:21:41 -05:00
Schuyler Eldridge 75fb99fa4e
[Support] Simplify Namespace.h Storage, NFC
Change Namespace.h to use a single, unified StringMap instead of a
StringSet and a StringMap.  This removes storage of duplicate keys in
two equivalent datstructures.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-12-30 14:43:55 -05:00
Hideto Ueno 716a7079a9
[ExportVerilog] Add IndexedPartSelectInoutOp to `isExpressionAlwaysInline` (#2406)
This commit adds IndexedPartSelectInoutOp to `isExpressionAlwaysInline`
which was missing.
2021-12-30 12:18:32 +09:00
Chris Lattner bc6666edaf [ExportVerilog] Fix wire indent level at top level, Issue #2363
This was a bug introduced in d458623.  Thanks to Hideto for the
nice testcase!
2021-12-29 10:56:53 -08:00
Morten Borup Petersen 1a5d106d14 [StandardToHandshake] Simplify setControlOnlyPath 2021-12-29 16:16:55 +01:00
Hideto Ueno 81641fc79a
[GrandCentral] Allow AugmentedGroundTypeAttr to annotate aggregate types (#2398)
This commit allows us to annotate AugmentedGroundTypeAttr to non-ground
types. First, I changed the element type of leafMap to be FieldRef
so that we can annotate to subelements. And `computeField` and
`traverseField` are modified to traverse the path represented by `fieldID`.
2021-12-29 17:04:30 +09:00
Hideto Ueno fd43dbc617
[HWCleanup] Change the order of simplifications (#2403)
This commit changes the visiting order of simplifications to handle
nested regions properly. Currently `runOnGraphRegion` executes the
following procedure:
```
for op in body:
    recurseToSubegions(op)
    mergeIfPossible(op)
```
This commit modifies the procedure like this:
```
for op in body:
    mergeIfPossible(op)
for op in body:
    recurseToSubregions(op)
```

This effectively handles nested regions. Interestingly, this also
makes `opsToRevisitRegionsIn` unnecessary because we merge
the outer level first.
2021-12-29 11:08:28 +09:00
Hideto Ueno 2eea30198f
[FIRRTL] Add multibit_mux op and lowerings (#2392)
This commit adds new operation `multibit_mux` to make 
subaccess lowering more efficient. Subaccess ops are 
currently lowered into mux chains but in HW/Comb dialect
they are pulled back to `array_create` + `array_get`. 
`multibit_mux` will be directly lowered into `array_create`
+ `array_get` at LowerToHW.

This commit containts parser/printer, folder, LowerTypes 
and LowerToHW change. `multibit_mux` operations are
created only at subaccess lowering in LowerTypes.

This speeds up entire process after LowerTypes 5%~10%
for large circuits.
2021-12-28 16:54:41 +09:00
Hideto Ueno 2efe26ee18 [LowerTypes][FIX] Make aggregate preservation more conservative
This commit makes aggregate preservation more conservative.
There are basically two changes: Previously bitcast was
fine to preserve aggregates but it breaks the compile if
`repl-seq-meme` is enabled. This issue is yet to be reduced but it
should not break the compile so I would like to make conservative
here. Another thing is the preservation of aggregate types with
zero-bit width(zero-bit integer or empty vector/bundle).
This is causing tedious downstream issues about zero-width struct
emissions in ExportVerilog so I would like to change not to emit
these things at all.
2021-12-27 23:28:42 -08:00
Hideto Ueno ef6424c5a1
[firtoo] Move HWCleanup after canonicalizer (#2395)
Some canonicalizers create new sv.if ops. As a result,
we get redundant if statement in output verilog.
This commit fixes the issue by moving HWCleanup to the later.
2021-12-28 12:23:46 +09:00
Mike Urbach 13948d32d8 [MSFT] Remove SwitchInstanceAttr and RootedInstancePathAttr.
These attributes and their use cases are now replaced by
hw::GlobalRefOp and hw::InnerRefAttr, respectively.
2021-12-27 13:52:14 -07:00
Mike Urbach a2a058b70e [MSFT] Refactor placement export to use hw::GlobalRefs.
This refactors ExportQuartusTcl to use the hw::GlobalRefs and arrays
of hw::InnerRefAttrs directly. This greatly simplifies the
implementation, and removes the need for SwitchInstanceAttr. That
attribute will be fully removed in a follow up.
2021-12-27 13:51:57 -07:00
Mike Urbach 737d474872 [MSFT] Refactor placement entry to use hw::GlobalRefs.
This replaces the use of msft::SwitchInstanceAttr on leaf entities
with a hw::GlobalRefOp. The global ref specifies the same path, using
an array of hw::InnerRefAttrs. It also has an attribute containing the
same placement information as the msft::SwitchInstanceAttr had.

This will simplify ExportQuartusTcl by letting it simply generate Tcl
referring to the hw::GlobalRefs. It will also make the placements
robust to changes in the instance hierarchy via the guarantees
provided by hw::GlobalRef's verifier and utilities for rebuilding
hw::GlobalRefs.
2021-12-27 13:51:32 -07:00
Julian Oppermann a51080a577
[Scheduling] Implement de Dinechin's "fast" modulo scheduler. (#2397) 2021-12-27 21:35:04 +01:00
Mike Urbach 6d7e0e9118 [HW] Add Python bindings for GlobalRefAttr.
This adds the necessary CAPI boilerplate and a basic Python type for
holding GlobalRefAttr.
2021-12-27 11:32:05 -07:00
Mike Urbach 9f7a01a865 [HW] Add Python bindings for InnerRefAttr.
This adds the necessary CAPI boilerplate and a basic Python type for
holding InnerRefAttr.
2021-12-27 11:32:05 -07:00
Julian Oppermann c5c8f79152
[Scheduling] Prepare simplex implementation for the modulo scheduler. (#2396) 2021-12-27 19:29:24 +01:00
mikeurbach a15a2c97d8
[SCFToCalyx] Initial support for PipelineWhileOp. (#2389)
This adds the necessary support for PipelineWhileOp in the
WhileOpInterface. It also adds basic support for lowering the
PipelineTerminatorOp and PipelineStageOp. Together, this enables the
PipelineWhileOp condition, iter args, and results to be converted.

Building pipeline registers and scheduling groups to pass values
between pipeline stages will be added as follow up work.
2021-12-27 10:52:29 -07:00
Prithayan Barua 521f7a3273
[HW] Add a new op HW::GlobalRef, to replace the FIRRTL::NonLocalAnchor (#2312)
Add a new operation `GlobalRef` to `HW` dialect, that will eventually replace 
`FIRRTL::NonLocalAnchor`. 
`GlobalRef` can be used to identify a unique instance path of an operation globally.

This is part of the plan to move the `firrtl.nla` to `HW` dialect.
2021-12-27 07:03:26 -08:00
Hideto Ueno 5bd8d8e82f
[SVExtractCode] Add missing assert operations (#2379)
SFC regards printf operations whose messages have specific prefixs
like "assert:", "assume:" or "cover". Most of them are converted into
builtin assert/assume/cover by FIRPaserAsserts but if the format is 
"ifElseFatal", assertions are lowered into sv.error + sv.fatal.  We have to
parse the error message again to regard such sv.error ops as assertions.
2021-12-27 20:41:25 +09:00
Hideto Ueno eeb73489ba
[FIRRTL] Make foldWhenEncodedVerifOp handle PrintOp even when they are not at a block begin (#2388)
This commit first moves `foldWhenEncodedVerifOp` logic into post parse
processing to restructure operations without fear. Next, foldWhenEncodedVerifOp
is modified to handle printf op not at block's begin. For example,

```scala
circuit Foo:
  module Foo :
    input cond: UInt<1>
    input enable: UInt<1>
    input io : {clock:Clock}
    when cond :
        printf(io.clock, enable, "assert: bar")
```

`circt-translate --import-firrtl` now generates expected IR.

```
firrtl.module @Foo(in %cond: !firrtl.uint<1>, in %enable: !firrtl.uint<1>, in %io: !firrtl.bundle<clock: clock>) {
  %0 = firrtl.subfield %io(0) : (!firrtl.bundle<clock: clock>) -> !firrtl.clock
  %1 = firrtl.not %cond : (!firrtl.uint<1>) -> !firrtl.uint<1>
  firrtl.assert %0, %1, %enable, " bar"  {eventControl = 0 : i32, isConcurrent = true}
}
```
2021-12-27 20:36:53 +09:00
Morten Borup Petersen 853cd4eb3b [NFC][SCFToCalyx] Tiny comment change 2021-12-26 10:37:23 +01:00