In llvm submodule: set branch to main, so can just update with:
$ git submodule update --remote --merge
See PR for summary of significant upstream changes and details of how they were handled:
https://github.com/llvm/circt/pull/3502
* AddSeqMemPorts: Add statistic for ports added.
* FlattenMemory: stat for memories flattened
* LowerMemory: stats for memories lowered and mem mods created.
* Dedup: nit, prefer preincrement
* LowerCHIRRTL: stats for mems lowered/created/portless (dropped)
* InferRW: stat counting memories inferred to rw port
* MemToRegOfVec: Add stat for mems converted.
This PR modifies LowerTypes to specify types preserved by aggregate preservation, i.e. `-preserve-aggregate={none, 1d-vec, vec, all}`.
Implementation wise, `peelType` takes the enum and selectively lower types.
This commit adds an option `emit-chisel-asserts-as-sva` to emit chisel
asserts as SVA assertions at LowerToHW. Users sometimes want to emit
only SVA for verification purpose and therefore, this commit provides a
command line option to emit "ifElseFatal" style assertion as SVA.
Adds a new `HWMutableModuleLike` op interface which exposes a bunch of methods which were all present in the `hw` operations which implemented `HWModuleLike`. This allows one of the ESI passes to not have knowledge of any `hw` module or instance ops -- it can operate on anything which has a module implementing `HWMutableModuleLike`. Paves the way to supporting `msft.module`.
We cannot directly switch to prefixed only because of the use of duck-typing in HWOpInterfaces.td and SVOps.cpp. This means we need to generate both the prefixed and non-prefixed accessors until all dialects that make use of HWInstanceLike have switched. This includes HW, SV, FIRRTL, MSFT.
This replicates some assertions implemented in the SV dialect. We need
to move these into the FIRRTL dialect so that they may be removed before
`IMDeadCodeElim` runs.
Co-authored-by: Hideto Ueno <uenoku.tokotoko@gmail.com>
We need to add a comment `// VCS coverage exclude_file"` to all Grand
Central modules and interfaces. When we needed something like this
previousl, it was previously handled by adding a `comment` attribute
onto `hw.module` and handled in lower to HW.
To support these new targets, we have to:
1. Add a comment attribute to SV interfaces. To accomplish this, I used
an optional string attribute. I switched the printed format to print
the attribute dictionary after the symbol name, which I think is more
common across all our operations.
2. Update ExportVerilog to print this attribute. The `emitComment`
function can recognize null attributes and skip a comment.
3. Propagate a "comment" attribute on FIRRTL modules in LowerToHW to HW
modules. This was not added to the ODS arguments, similar to the
`output_file` attribute.
4. Modify GrandCentral to attach these comments to generated modules and
interfaces.
I tested this on a design and there were no more files in the `scope`
directory missing this attribute.
Co-authored-by: Hideto Ueno <uenoku.tokotoko@gmail.com>
Implements a pass to connect up ESI services clients to the nearest server instantiation. Wires up the ports and generates a generation request to call a user-specified generator.
Add Annotation class names associated with the "Full Async Reset
Transform" (which is implemented by the InferResets pass) to the global
AnnotationDetails.h definitions file. Use these definitions in place of
strings in InferResets.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add MustDeduplicateAnnotation to Annotation definitions and use it in
place of a string in the Dedup pass.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Drop RunFirrtlTransformAnnotations in the LowerAnnotations pass. This
is an Annotation that is used to add passes to the Scala FIRRTL
Compiler (SFC) pass pipeline and has no use in CIRCT.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
ESI global services provide connectivity to chip-level stuff like PCIe, DRAM, Ethernet, etc. Additionally, services are completely user-defined and can be used recursively, so a user could define a telemetry service which is backed by PCIe (for instance). Users need to implement the services themselves, but ESI will plumb through the connection requests and provide users with a list of pre-connected ESI ports. ESI could also provide several standard multiplexing components.
Implements roughly the model in #2811. A lowering pass as described in the op documentation will be in a subsequent PR.
Add utilities and verifier for InnerSymAttr.
Add utilities to,
1. Get sym name for a field ID
2. Check a property for all field IDs
3. Get number of symbols
The verifier checks that,
1. All the fieldIDs specified are unique.
2. All the inner sym names are unique.
3. The fieldID is valid.
4. For ops with zero or multiple results, only the fieldID=0 can have
an inner sym.
Towards https://github.com/llvm/circt/issues/3430, this PR implements
generic SV attributes which are allowed to be attached to arbitrary expression.
1. Disable some SV canonicalizers to keep sv attributes. Canonicalizations
of comb and hw are not blocked in this PR (maybe necessary in the future).
2. HWCleanup cannot merge operations if there is a SV attribute.
3. Currently ExportVerilog emission is implemented for only
reg, wire, assignments and hw.array_get to reduce the complexity of
this PR. When SV attributes are attached to unsupported ops,
ExportVerilog emits errors.
4. Python bindings are also modified
This PR removes the canonicalization introduced by https://github.com/llvm/circt/pull/965 which is
incorrect under 4-values logic. `reg <= cond ? foo: reg;` is not equivalent to `if(cond) reg <= foo` when `cond` is `x`.
Add global definitions of InlineAnnotation and FlattenAnnotation and use
them in the ModuleInliner pass.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add a global annotation definition for NestedPrefixModulesAnnotation and
use this in the PrefixModules pass.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add a missing Annotation definition, PrefixInterfacesAnnotation. Use
this in the Grand Central Views pass instead of a bare string.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Delete testbenchDirAnnoClass Annotation definition in favor of
testBenchDirAnnoClass. Both variants were accidentally defined.
Replace uses of the former with the latter.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Change the CreateSiFiveMetadata pass to use globally-defined Annotation
class names. Add any missing Annotation class name definitions from
this pass.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
`PassCommon` contains `getAndSortModules`, which is generally useful. Make it general by implementing `HWModuleLike` and `HWInstanceLike` and targeting those OpInterfaces instead. Involves a bit of ugliness when converting to/from the OpInterfaces to concrete module ops, but hopefully that'll go away as we add more functionality to said OpInterfaces.
This commit adds support in `sv.case` for switching on enum values. In doing so, a fair bit of refactoring is done to `CasePattern`s to more cleanly handle the different cases of bit, enum, and default patterns.
Since `hw.enum` doesn't yet include any notion of value encoding, the `sv.case` operation exclusively works on either enum or bit pattern.
Furthermore, only a single case value can be compared in a case statement (as opposed to `case A, B : ...`). I think this is a good starting point - if support is needed in the future, it will not be complicated to add.
```mlir
hw.module @AnFSM(%clock : i1) {
%reg = sv.reg : !hw.inout<!hw.enum<A, B, C>>
%reg_read = sv.read_inout %reg : !hw.inout<!hw.enum<A, B, C>>
%A = hw.enum_get #hw.enum.value<A, !hw.enum<A, B, C>>
%B = hw.enum_get #hw.enum.value<B, !hw.enum<A, B, C>>
%C = hw.enum_get #hw.enum.value<C, !hw.enum<A, B, C>>
sv.always posedge %clock {
sv.case case %reg_read : !hw.enum<A, B, C>
case A : { sv.passign %reg, %B : !hw.enum<A, B, C> }
case B : { sv.passign %reg, %C : !hw.enum<A, B, C> }
default : { sv.passign %reg, %A : !hw.enum<A, B, C> }
}
}
```
emits
```systemverilog
module AnFSM
enum {A, B, C} reg_0;
always @(posedge clock) begin
case (reg_0)
A:
reg_0 <= B;
B:
reg_0 <= C;
default:
reg_0 <= A;
endcase
```
Will Dietz