* [HandshakeToFIRRTL] Add MemoryOp lowering.
This adds a basic lowering from MemoryOp. The appropriate
data signals are connected and the control signals are built
similarly to the ForkOp and JoinOp. The memory uses a read
latency of 0, a write latency of 1, and returns the old value for read
under write. This is part of https://github.com/llvm/circt/issues/337.
The lint integration test which was supposed to be testing this wasn't
being emitted. Fixed that and discovered warnings.
I *think* the packed dimensions were being emitted backwards. Someone
please check me on this.
It wasn't pulling its weight and added more complexity than it saved.
See the rationale doc for more information, as well as why sext still
makes the cut.
1. Update LLVM submodule
2. Update circt-translate help message
New version of MLIR properly prints the help message. This updates the
command line test for it.
3.Do not use methods from OpState that just forward to Operation
These methods are being removed from mlir::OpState in reviews.llvm.org/D94191
3. Use standard integer types in LLHDToLLVM
The type system for the LLVM dialect is undergoing changes to use types
from the standard dialect. This includes the removal of LLVM integer
types, removal of the common parent type LLVMType, new helpers for
working with LLVM structs, arrays, and pointers.
for more information see:
reviews.llvm.org/D94178
reviews.llvm.org/D93680
reviews.llvm.org/D93713
The getPossiblyInoutLoweredValue contract is now much simpler, because
the stdintcast and analog cast operations don't pass non-FIRRTL operands
into them.
Change the testcase to align with what is produced by LowerToRTLModule now.
We need the handle zero-bit outputs specially because we cannot
materialize a zero bit value at the RTL level (we don't have anything
like undef or poison), so we promote them to inout values.
Since the lowering is the same for all primitives, we handle it
centrally, rather than making them all think about it.
This also checks in the testcase I forgot to git add.
FIRRTL has many operations that implicitly extend their operands to
a result width. When the input has zero bits and the extended
destination is larger, then the resultant value is zero. Implement
this, which is enough for Issue #328.
Zero width type support is still not complete, more to come.
During parsing, optionally convert a register's clock, reset, or
initialization to a passive type if it is a sink. This causes CIRCT to
now accept circuits which the Scala FIRRTL Compiler (SFC) also
accepts.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This reverts commit ad023e876b.
Verilator complains (erroneously) about the width when an ADD is inside
the array slice. It doesn't when the expression is declared out-of-line.
Use the convertToPassive utility two additional places in the parse
instead of duplicating the implementation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Before we had a division of the force between FIRRTL and RTL. Now that
everything is consistent, they don't need to be a special case. This
removes a bunch of code.
Merge emitBitSelect into its only caller. Eliminate the duplicate
logic between "measuring" and "printing" of typedims, by printing to
temporary strings, measuring them, then ultimately emitting the string.
This changes listconcat to use #, and uses string quotes more in
cases instad of [{}]. Thanks to Paul C. Anagnostopoulos for making
these cleanups possible.
During parsing, add an asPassive cast to a node argument if it is
passive under an outer flip. Error if type is analog or underlying
type is not passive. Restrict a NodeOp's input to be passive.
Enables parsing of weird CHIRRTL circuits where a node is a "sink" (an
output port or an instance input).
Add test cases of this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Shivam Gupta