This refactors the code a bit to split between procedural and graph
regions (which are semantically very different). This also changes
the merging code to merge "down" instead of "up" which doesn't matter
for graph regions but is required for procedural regions.
Before we'd use "!FOO" as an identifier to get an inverted conditional.
Such a representation gives us two different ways to represent the same
thing and unnecessarily makes transformations on ifdefs (like merging
of them) more complicated.
Instead just put inverted logic into the else block, and have the verilog
exporter print a ifdef with no "then" as ifndef.
This patch also merges the code I duplicated in the verilog emitter for
the two ifdef cases.
The former can be used in graph regions, the later in procedural regions.
The later is marked with ProceduralRegion trait, and will eventually have
different requirements about its parent region.
The previous calculation was done using the width of the entire 64-bit
index to dynamically shift a bit into a one-hot vector. This adds a
tail operation to only select the bits needed from the index. This
updates the decoder implementation to just compute the correct result
width of the dshl operation, and drops the unneeded pad.
It can be really helpful to disable the verifier in order to dump all of
the IR at a later point. This option is already supported by circt-opt,
but it can be useful here as well.
- Don't forward declare thread. Does not work on OSX, and in general
you can't forward declare classes from the `std` namespace.
- Fix namespace issues caused by e1ca6eaaf9.
- Fix cosim test: fix constants
This change aims to remove all instances of `using namespace mlir` from
our header files. Many types have been manually imported into the
`circt` namespace in `circt/Support/LLVM.h`. These types include all
core MLIR functionality types (IR, Diagnostic), utility types, rewrite
patterns and conversions, builtin IR types and attrs, and the module op.
Not imported were any operations (other than ModuleOp), matchers (e.g.
m_Zero), anything in the `impl` namespace, and interfaces. There are
some problems with interface code generation from ODS, so some
interfaces were imported.
Some further cleanup would be useful to remove the `mlir::` namespace
qualifier where we no longer need it.
This broke with the change to move instances to return multiple results.
This change also fixes the parser to handle "is invalid" on passive types
correctly.
It turns out these are completely different forms in the SV spec (wire is a net,
logic is a var decl). logic corresponds to what we actually need (single assignment
semantics) and can be used in nested blocks like an always, so we use it instead of
wire generally.
Explicit rtl.wire declarations and rtl.merge are still emitted as a wire of course.
This is progress towards issue #439.
This makes sure we emit wire declarations for expressions that have
multiple uses correctly, avoiding an exponential blowup of verilog
in some cases, and emitting expressions that have to go through an
intermediate wire declaration.
This is currently emitting wire declarations within always blocks,
which I'm not sure is valid. If not, I'll do a second follow up.
We need a token of lookahead to tell the difference between an expression
using the 'output' identifier and the output specifier in a port list. This
is a bit annoying to implement in the portlist parsing logic, so just add full
support for backtracking in the parser.
Switch from blocking assign to non-blocking assign in the always block
generated for a memory write port. This should fix one of the warnings
that Verilator generates as identified in issue #543.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Chris Lattner