* Revert "[Ibis] Split ContainerOp in two (#6739)"
This reverts commit d17f2f1a1b.
* [Ibis] Introduce 'ibis.design'
Encapsulate everything into a new op. It's an InnerSymbolTable so that
we can identify _everything_ with inner symbols.
Partial progress.
* Hopefully avoid some msvc warnings
* add topLevel attr to containerop
* bug fixes
* Nest createContainerizePass inside of <ibis::DesignOp>
* Work
* Work
* Working
* Self review
---------
Co-authored-by: Blake Pelton <blakep@microsoft.com>
Co-authored-by: Morten Borup Petersen <morten_bp@live.dk>
This PR adds a JIT runtime for arcilator, backed by MLIR's ExecutionEngine. This JIT allows executing `arc.sim` operations directly from the arcilator binary.
Fix a bug in the om-linker tool where the Emit dialect was not loaded.
This dialect needs to be loaded as Emit is already being used by
end-to-end compilation and by tools that facilitate this, e.g., firtool.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Removes:
- esi-cosim-runner.py
- all of the raw capnp based tests
- the system test (subsumed by other tests)
- cmake target esi-collateral
- runtime distribution from PyCDE
Move the call to `registerFromVerilogTranslation()` from the
`InitAllTranslations.h` header, where it is executed unconditionally,
into the `circt-translate.cpp` file, where it can more easily be guarded
behind an ifdef. This fixes builds with the Slang frontend disabled.
In the future we may want to generated a header with macros that reflect
which optional parts are enabled or disabled. `InitAllTranslations.h`
could then use those macros to conditionally register the ImportVerilog
translation.
Add the `ImportVerilogOptions` struct to capture various options that
can be passed to the Slang Verilog frontend. This covers things like
include search directories, macro definitions, top modules, time scales,
and other settings commonly found in Verilog tools. The struct is
inspired by `slang::driver::Driver::Options`, but we intentionally
create our own struct such that no Slang headers leak through into CIRCT
space.
Add corresponding command line options to `circt-verilog`, and use them
to populate an `ImportVerilogOptions` struct that can be passed to
`ImportVerilog`.
Add `importVerilog` and `preprocessVerilog` functions to `ImportVerilog`
and add corresponding options to `circt-verilog` that call the
respective import function. This commit only implements preprocessing.
This commit also adds a mechanism to bridge between the diagnostic world
of Slang and MLIR (`MlirDiagnosticClient`). This allows us to emit any
Slang-generated diagnostics as regular MLIR diagnostics, alongside any
other errors or warnings the Verilog import might generate.
Add tests for the preprocessor (with include paths and macros) and the
diagnostic bridge.
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Co-authored-by: ShiZuoye <albertethon@163.com>
Co-authored-by: hunterzju <hunter_ht@zju.edu.cn>
Co-authored-by: 孙海龙 <hailong.sun@terapines.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>
This is the first PR in a longer chain that adds basic SV support to
CIRCT.
Add the Slang Verilog frontend as a CIRCT dependency. This will be the
foundation for CIRCT's Verilog parsing, elaboration, type checking, and
lowering to the core dialects. By default, Slang is built as a static
library from scratch, which is then linked into the new `ImportVerilog`
conversion. Alternatively, CIRCT can also be linked against a local
Slang installation provided by the system.
Add the `ImportVerilog` conversion library. This library statically
links in the Slang dependency and wraps it in an exception-safe,
LLVM-style API. Currently this only consists of the `getSlangVersion`
function and the necessary linking flags to get it to link statically
against Slang.
Add the `circt-verilog` tool, which will provide a fully-flegded
interface to the new `ImportVerilog` library. Later on we'll also add an
MLIR translation library for single-file SV import. But in general, SV
builds take a lot of command line options (macros, search paths, etc.)
and multiple input files, which is why we have a dedicated tool. All the
tool does at the moment is print the linked Slang version. More to come.
Note that this intentionally links against **version 3** of Slang. Newer
versions are available -- 4 and 5 as of this commit -- but they rely on
fairly new C++ compiler features that didn't work out of the box in our
CI images. We'll eventually want to upgrade, but for now Slang 3 is
sufficient to get the ball rolling.
See https://github.com/MikePopoloski/slang for details on Slang.
Co-authored-by: ShiZuoye <albertethon@163.com>
Co-authored-by: hunterzju <hunter_ht@zju.edu.cn>
Co-authored-by: 孙海龙 <hailong.sun@terapines.com>
* Added missing tool in integration test
* Fixed formatting
* Fixed whitespace issue
* Fixed typo in VerilogGeneration.md
* Added skeleton for btor2 lowering pass
* added pattern match skeleton to lowering pass
* Added initial emission of inputs and hw::constant ops
* added constant emission
* added emission for most operations and final assertion
* Added support for muxes, assumptions and wire aliases
* Added support for inputs in btor2
* fixed bug in input generation
* added support for missing comb operations
* Changed input registration to allow for booleans
* Made input type check more robust
* WIP register state transition system generation
* Added support for registers
* refactored hardcoded string
* added names to btor2 states
* Added state initialization support
* Removed state initializer, it should be a firrtl construct and not a btor one
* Removed temporary file emission
* Added back accidentally removed btor2 string printing
* Ran clang-format
* Ran clang-format
* WIP refactored typeswitch
* refactored giant type switch
* Made all string litterals constexpr
* attempting to fix sanity check
* fixed variable name typo
* Attempting to satisfy clang-tidy
* renamed things to make clang happy
* inlined useless helper methods
* Clarified the necessity of important data structures in comments
* fixed formatting
* Changed pass into a Conversion pass
* refactored helper methods
* Checked for case where next is a port when emitted transitions
* Added newline at EOF
* Inherited visitors instead of using a big typeswitch
* Throw an error for unsupported ops and explicitly ignore the rest
* Removed unnecessary functions and refactored runOnOperation
* Fixed formatting
* Attempted to add some test
* Added in ops that weren't covered by visitors
* Added in missing declaration in header
* Included pass in CAPI CmakeLists
* Added infrastructure for btor integration tests
* Revert "Added infrastructure for btor integration tests"
This reverts commit a5ec3da4ec.
* various nitpicking comments accounted for
* used generalized ids for btor2 testcase
* fixed typo in test
* updated test and found small bug
* clang-format
* added support for arbitrary resets
* Updated test to reflect new handling of reset
* Switched to a DFS strategy for emission
* Updated test to align with preemission of register declarations
* Removed gratuitous lookups.
* inlined a bunch of string constatns
* removed certain silent fails and added out of order test
Enable the `InferStateProperties` pass in the arcilator pipeline and
make its enable and reset signal detection individually controllable.
The enable portion is already supported by the rest of the arcilator
pipeline and can produce 20%-35% speedup on the cores in arc-tests.
Turn on enable detection by default.
The reset portion is not fully supported yet and causes the simulation
to misbehave. It is disabled by default.
As a minor refactoring this removes the `constructor` field from the
pass definition, such that the constructor and plumbing for options gets
generated automatically. As a side effect, the constructor is now called
`arc::createInferStateProperties` instead of the previous
`arc::createInferStatePropertiesPass`. (Thanks @uenoku for the pointer.)
Shoutout to @maerhart and @TaoBi22 for this fantastic pass!
Instead of always making registers and memories observable for the user,
add dedicated `--observe-registers` and `--observe-memories` options to
`arcilator`. These allow the user to indicate whether they are
interested in observing or register and memory state. If these options
are set to false, don't attach "name" or "names" attributes to states
and memories, such that other parts of the pipeline have a chance to
delete unnecessary state.
Add an option to HGLDD file emission to only consider location
information in the IR if the corresponding file exists on disk. This can
help filter out placeholder filenames such as `<stdin>` or `<unknown>`.
Also add a corresponding `--hgldd-only-existing-file-locs` option to
firtool.
Remove the -scalarize-top-module option to firtool (and the parser).
Replace this with -scalarize-public-modules. This is done in preparation
for FIRRTL 4.0.0. This is also largely unnecessary once FIRRTL 4.0.0
figures out how to attach the ABI to each public module.
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Move firtool pipeline configuration over to the same mechanism the rest of llvm and mlir use. Export this via the CAPI. Add a couple examples of methods to change options to the CAPI. Interested parties are encouraged to finish out the set of functions.
Since the CAPI has no tests, this breaks nothing.
As an aside, the configuration space of the firrtl pipeline is WAY too big.
Rather than identifying cosim endpoints by "%m", have them specified entirely upstream. The easiest way to ensure uniqueness then is to only allow cosim endpoints at the top level. This solves a number of issues, and also makes cosim look a lot more like other ESI services.
The pass relies on `seq` items, creating a circular dependency between SV and Seq.
It better belongs to the seq dialect, alongside options and ops it related to.
Moving forward, this should be merged into FIR memory lowerings.
Add the `MaterializeDebugInfo` pass, which creates debug ops to track
FIRRTL-level ports, nodes, wires, registers, and instances throughout
the pipeline. This is a fairly simple first attempt at tracking
higher-level source language information through the compilation using
the debug dialect.
Also add the `-g` option to firtool, which causes this pass to run very
early on in the pipeline where all the high-level information is still
available. Enabling this option will currently cause `ExportVerilog` to
fail because of the additional operations in the IR -- to be rectified
by a later PR.
Add the `dbg` dialect, alongside a rationale document, basic types, and
the three essential `dbg.variable`, `dbg.struct`, and `dbg.array`
operations.
The goal is for this dialect to be a home for all the machinery needed
to track debug information in the IR. After discussions with a few
people in the LLVM/MLIR space, I chose to create dedicated operations to
track debug info in the IR, as opposed to an attribute/metadata based
approach. The details are outlined in the rationale document.
Subsequent PRs add simple debug info tracking to FIRRTL and firtool, and
extend debug info emission to consider these operations.
Amelia Dobis