* [FIRRTL] Correct RegInitOp description
Fix copy-paste typo where the description of RegInitOp uses the "reg"
keyword instead of "reginit" keyword.
* [FIRRTL] Enforce register op clock is a clock type
Change the type of the clock connection for RegOp and RegInitOp from
AnyType to ClockType.
* [FIRRTL] Add checks the register clock is a clock
Add tests for RegOp and RegInitOp that the type of the clock
connection is actually a clock.
* [FIRRTL] Add FIRRTLType.isResetType
Add a method that determines if a FIRRTLType is a valid reset type. A
valid reset is one that is either an abstract reset, a concrete 1-bit
UInt, or a concrete asynchronous reset.
* [FIRRTL] Add constraints to ResetType
Use new FIRRTLType::isResetType to assert that a ResetType is actually
a valid reset type.
* [FIRRTL] Require RegInitOp reset is ResetType
Change the required type of the reset connection in a RegInitOp from
AnyType to ResetType. This relies on constraint checking of ResetType
and will accept any abstract reset, concrete asynchronous reset, or
concrete 1-bit UInt.
* [FIRRTL] Test rejection of bad RegInitOp resets
Add a test that a 2-bit UInt reset connection is rejected as invalid
FIRRTL.
Mostly this fixes changes in how APInt is used for op and builder interfaces.
Overall, we are able to remove extra APIs that used to exist to provide int/unsigned
native type interfaces.
* [FIRRTL] Fix tests so "main" matches a module
Fix FIRRTL tests to make them valid FIRRTL IR. Previously, the example
FIRRTL IR or FIRRTL MLIR dialect examples could contain a circuit
whose name (what FIRRTL IR calls the "main" or, equivalently, the top
module) did not match the name of a module in the circuit. This commit
changes the tests so that this invariant holds.
* [FIRRTL] Add circuit verifier
Add a new function, verifyCircuitOp, that is used to verify a FIRRTL
circuit op. This checks the following two conditions:
1. The circuit must have a name ("main" in FIRRTL IR/the top module)
2. The circuit must contain a module matching the circuit name
This brings the FIRRTL dialect in line with the current implementation
of the FIRRTL compiler where condition (1) is nonsensical and
condition (2) is rejected.
* [FIRRTL] Test circuit verifier
Add a test for the FIRRTL dialect that the user is provided with an
error if they provide FIRRTL MLIR whose name (it's "main" or top
module) does not match the name of any modules in the circuit.
Add a test that the FIRRTL dialect circuit op has a non-empty name.
This picks up some enhancements to ODS, as well as a few changes:
* Dialect registration is being updated. For now, the global dialect
registry is enabled for backwards compatibility while we update
the dialect registry mechanisms
* Kinds are removed from Types and Attributes. This is a mostly
mechanical change to use isa and TypeSwitch
* Generated passes are registered differently. The approach here is
to define the registerPasses function in an anonymous namespace
and call it from within the existing static helpers.
* Upstream LLVM dialect has updated how types are printed, and the
LLHDToLLVM tests are updated accordingly
must be emitted out of line (due to verilog language limitations).
This allows us to get the entire verilog-basic.fir testcase through
the LowerToRTL/EmitVerilog path. Not all constructs are supported
though.
their terminator. This makes the builder->build<IfOp>() construct work
better.
This is something that ODS should arguably do in general, I'll file an
enhancement request.
* [LLHD] Add memory to block argument promotion pass
* Promote memory locations allocated with llhd.var to block arguments to allow further optimizations.
* This pass is also required to lower behavioral LLHD to structural LLHD, because all control-flow has to be eliminated and structural LLHD has no memory model
* For this version pointers may not be used in operations apart from llhd.load and llhd.store, it may also not be created by a function call.
* It is limited to llhd.proc for now as functions have to be completely inlined for the lowering anyways
* There may not be any operations with nested regions in llhd.proc which are not isolated from above. This only affects the llhd.for operation which has to be completely unrolled for the lowering anyways
* Some of those restrictions can be lifted in a future commit
* Fix typos and better data structures
* [LLHD] Add folders and canonicalization patterns for extract operations
* Use m_Constant pattern to match constant value
* Remove unnecessary includes
* Use tablegen patterns to canonicalize dynamic extract operations
if/ifdef/always @ posedge, fwrite, and macro expressions.
This is still very simple and early on, but is a reasonable starting
point to expand the capabilities for the verilog printer.
* This pass moves all instructions without side-effect and llhd.prb as
far up in the CFG as possible as preparation for the Temporal Code
Motion pass and to enable total control-flow elimination
* This also includes a Temporal Region analysis to evaluate which blocks
are guaranteed to execute at the same physical time. This is needed to
move llhd.prb instructions as they are not allowed to be moved to
blocks which could be executed at another physical time and thus probe
an older or newer state of the signal. It will also be needed for the
Temporal Code Motion pass and Desequentialization
* Update LLVM version to c89e46e76
A small fixup is required to avoid conflicts between ODS-generated build
methods because of default arguments. Also, since this keeps failing, I've
updated the llvm cache so that it runs in a separate job. Otherwise the cache is not updated when the CIRCT build fails.
* [LLHD] Add `SigType` conversion
* [LLHD] Add time type and constants conversion
Previously time constants were converted by their users, by creating a constant for each of the three time attributes. This makes time constants LLVM arrays containing the three time values instead, allowing more a more flexible use (e.g. passing time operands as block arguments).
* Add time type conversion.
* Add tme constants conversion.
* Add time operands to the process persistence state.
* Fix affected tests.
* [LLHD] Set LLVM::DialectCastOp as legal during `InstOp` lowering
This works around the PartialConversion failing because of the introduction of (unused) `DialectCastOps`, that will be dealt with later during the full conversion.
Co-authored-by: rodonisi <simon@rodoni.ch>
* [LLHD] Improve simulator signal representation
Previously signals lowered to the LLVM dialect where represented as just an index in the state's global signal table. That required to query the state to gather the signal information for each signal, and also to store temporary subsignals in the state itself. This improves how signals are represented in the lowered code and state:
* Directly represent signals in the lowered code as a pointer to the detail struct, containing the signal's information. This allows to represent subsignals without adding them to the state.
* Directly pass the list of detail structs as a function argument to the lowered unit function, instead of a list of indices. This allows to get rid of the runtime function that was used to query the state for that info.
* Merge the signal, input and output tables in the instance state. This distinction is not required here and added unnecessary complexity. This also fixes a wrong behavior, where instances did not get triggered by changes in output signals.
* Use the `SignalDetail` struct for instance signal tables directly,
instead of indices.
* Adjust affected tests.
* Add outputs to process sense table
As discussed with Chris Lattner in #54, this was always the intent.
The file include/circt/Dialect/FIRRTL/Passes.h already indicated the LLVM exceptions
apply.
This will be posted to discourse. If you are a significant contributor and
object, we need to hear from you.
* add clock and reset signals to create*ModuleOp() function
* add BufferOp to HandshakeOps.td
* add insertBufferOps() method
* add -insert-buffer pass for handshake
* add test_insert_buffer test case
* update references and remove the real stack structure
* support sequential submodules
* add initial buildBufferLogic() method
* add attribute to buffer operation
* fix small issues, and mechanical rename all passes from DF to Handshake
* update createInstOp() and getSubModuleName() for supporting sequential modules
* add test_buffer.mlir test case
* add test_buffer.mlir test case
* support multiple clocks; fix small issues
* [LLHD] Add memory type and operations
* Add `llhd.ptr<T>` type to represent pointers LLHD types.
* Add var (allocate stack space with an initial value), load and store operations.
* Rename `LLHD_AnySigUnderlyingType` -> `LLHD_AnyUnderlyingType` in `LLHD.td` as this can be shared between signal and memory operations.
* Add test case for memory operations.
* Two-space indents
* Remove NoSideEffects
* Add memory SideEffects traits
* Change `ptr` -> `pointer` in type description
* Add memory `cse`/`dce` test
* Use sentence fragments for Arg/Res description
* Add missing line at end of file
* Add folders for bitwise operations
* Fold bitwise operations having complements as arguments
* Fold double not
* Convert xor with one operand being all ones to a not
* Add equality operation canonicalization patterns
* Move shift folding tests to new canonicalization folder
* Merge old bitwise and arithmetic folding tests
* Add newlines
* clang-format
Schuyler Eldridge