Commit Graph

8794 Commits

Author SHA1 Message Date
John Demme 5bc663c446 [ESI][Runtime] Minor cleanups
- Got an integration test which wasn't running working.
- Fixed a pybind11_stubgen error.
- Fixed an AppID constructor warning.
- Mitigated a poor hash function.
2024-08-08 12:21:02 +00:00
John Demme ad91378465
[ESI][Runtime] Poll method and optional service thread polling (#7460)
Add a poll method to ports, a master poll method to the Accelerator, and the ability to poll from the service thread. Also, only spin up the service thread if it's requested.

The service thread polling (in particular) required some ownership changes: Accelerator objects now belong to the AcceleratorConnection so that the ports aren't destructed before the service thread gets shutdown (which causes an invalid memory access). This particular binding isn't ideal, is brittle, and will be an issue for anything doing the polling. Resolving #7457 should mitigate this issue.

Backends are now _required_ to call `disconnect` in their destructor.
2024-08-08 03:53:42 -07:00
Morten Borup Petersen caab217642
[ESI] Add option to build runtime as a static library (#7455)
* [ESI] Add option to build runtime as a static library

* review comments

---------

Co-authored-by: Morten Borup Petersen <mpetersen@microsoft.com>
2024-08-08 11:02:19 +02:00
Hideto Ueno 12822ad0d0
[SimToSV] Add include guards to DPI import (#7459)
This adds include guards `__CIRCT_DPI_IMPORT_*` to DPI import statements generated in SimToSV. 

Fix https://github.com/llvm/circt/issues/7458.
2024-08-08 15:40:35 +09:00
Hideto Ueno a9436263bd
[ExportVerilog] Add a lowering option to fix up empty modules (#7454)
This commit adds a new lowering option to sanitize empty modules by
creating a dummy wire in it.
2024-08-08 15:39:05 +09:00
Fabian Schuiki 1d417e2d30
[FVInt] Add resizing utilities, allow hashing
Add more utilities to help with resizing `FVInt`s, including

- counting the active bits for signed and unsigned interpretation
- truncation
- zero/sign extension

Also add a default constructor that produces a zero-bit zero value,
allow `FVInt`s to be hashed, and consider bit width for equality
comparisons.
2024-08-07 17:53:24 -07:00
Fabian Schuiki aae791b1e9
[FVInt] Fix printing when bit width is less than one full digit
Printing of `FVInt`s would continuously shift the value right by the
log2 of the radix. This triggers an assertion in `APInt` in the case
where the bit width is less than the number of bits being shifted.
2024-08-07 17:53:24 -07:00
Schuyler Eldridge fcdefe5a1a
[FIRRTL] Whitespace cleanup, NFC
Fix a trailing double newline.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-08-07 20:40:45 -04:00
Schuyler Eldridge c08ac4bd78
[FIRRTL] Cache symbol table in LowerLayers (#7436)
Precompute a symbol to layer mapping inside LowerLayers and uses this
instead of a symbol table.  This is both faster and avoids problems of
trying to compute a symbol table while modules may be created.

Repurpose the functions that were being used to create macro declarations
to also compute this symbol to layer mapping.  Rename these to indicate
that they are now doing generic layer preprocessing.

Fixes #7434.

h/t @youngar for the fix suggestion.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-08-07 11:50:05 -04:00
Hideto Ueno cadbfe0e5e
[circt-lec] Accept two MLIR inputs (#7450)
Practically it is very useful to verify equivalence between modules in two different MLIR files. This commit changes `inputFilename` to a list and implements a very simple module merge that moves operations in the second module to the first by resolving the symbol.
2024-08-08 00:21:51 +09:00
Leon Hielscher 07179af7d9 [NFC] Remove trailing whitespace 2024-08-07 17:03:40 +02:00
fzi-hielscher 30ed753d53
[arcilator] Add JIT runtime environment library and stdio hooks (#7445) 2024-08-07 16:06:30 +02:00
Hideto Ueno 4c215e8ab8
[arcilator] Add an option to load shared lib into JIT engine (#7453)
This PR adds an option `--shared-libs` to load shared lib in the JIT engine in a similar way to what circt-lec does for loading z3 shared lib. With this change DPI library could be linked in arcilator.
2024-08-07 21:16:12 +09:00
Hideto Ueno 9828707817
[Arc][Sim] Lower Sim DPI func to func.func and support dpi call in Arc (#7386)
This PR implements initial support for lowering Sim DPI operations to Arc. 

* sim::LowerDPIFuncPass implements lowering from `sim.dpi.func` to `func.func` that respects C-level ABI. 
* arc::LowerStatePass is modified to allocate states and call functions for `sim.dpi.call` op. 

Currently unclocked call is not supported yet.
2024-08-07 13:51:14 +09:00
jpien13 1a8f82e7a6
[FIRRTL] Replaced 'replicate' to correctly named 'replace' flags (#7442)
Renamed and replaced shouldReplicateSequentialMemories to shouldReplaceSequentialMemories per issue #7384
2024-08-06 14:47:47 -07:00
Will Dietz 1645d71c1d
[FIRRTL] Tweak printing of layers to avoid extra space. (#7449)
Before:

firrtl.layer @A  inline

After:

firrtl.layer @A inline
2024-08-06 11:25:28 -05:00
Martin Erhart cac5b3a285 [SMT] Add convenience builder 2024-08-06 17:10:54 +01:00
Will Dietz 4415b9c2f7
[FIRRTL] Verify RWProbeOp target has layer requirements. (#7372)
RWProbe conservatively means a write to the target, so check
that the target is indeed writeable from where the rwprobe is.
2024-08-06 11:03:10 -05:00
Morten Borup Petersen 0b93783aae
[Ibis] Don't include design name in namespace in IbisContainersToHW (#7425)
The ibis.design op will be removed after the IbisContainersToHW pass, and there may be ibis.component's inside the design that have the same name as the design; we want that name to persist, and not be falsely considered a duplicate.

Co-authored-by: Morten Borup Petersen <mpetersen@microsoft.com>
2024-08-06 17:34:41 +02:00
Will Dietz de281de5de
[FIRRTL] Verify main module is a module, and is public. (#7439)
Add tests for new errors and existing error (changed).

Op errors should remember to make sense when read prefixed
with "mydialect.opname op ".
2024-08-06 08:00:16 -05:00
Morten Borup Petersen fd2b37acfd
[Support] Allow erasing names in Namespace (#7424)
* [Support] Allow erasing names in Namespace

Allowing erasing names in a namespace seems more sane than micro-managing which names gets added to a namespace. E.g., it's convenient to use `Namespace::add(SymbolCache &` to efficiently prime a namespace, and then surgically removing some known identifier,, instead of having to re-implement how symbols are added to the namespace.

* Add lock

---------

Co-authored-by: Morten Borup Petersen <mpetersen@microsoft.com>
2024-08-06 14:28:36 +02:00
cepheus 930aabe70f
[CMake] Fix install failure with CMAKE_SLANG_FRONTEND_ENABLED enabled (#7437)
Slang compiler relies on the third-party libraries like unordered_dense and fmt
library. The fmt library provides two ways to integrated it:
  1.Headers-only
  2.Seperately compiled
The main purpose of this commit is to avoid installation failure of CIRCT project due
to finding fmt header file in wrong path which is in circt `include` directory when
CMake_slang_Frontend_enabled is turned on. We hope to not install header files coming
from fmt library.
2024-08-06 11:29:30 +08:00
Asuna b35bc81fc0 [Docs][FIRRTL] Build and include docs for intrinsic ops 2024-08-06 10:36:05 +08:00
Fabian Schuiki 5cc69bd6b1
[ImportVerilog] Switch from SCF to CF dialect for control flow (#7432)
Instead of using the SCF dialect and its `scf.if` and `scf.while`
operations for control flow, switch over to the CF dialect and its
`cf.br` and `cf.cond_br`. This allows us to support SystemVerilog's
`continue`, `break`, and `return` statements which don't map well to the
Structured Control Flow dialect.
2024-08-05 17:10:19 -07:00
Will Dietz bec0deab4b
[Python][OM] Handle BoolAttr's before IntegerAttr's. (#7438)
BoolAttr's are IntegerAttr's, check them first.

IntegerAttr's that happen to have the characteristics of
BoolAttr will accordingly become Python boolean values.

Unclear where these come from but we do lower booleans
to MLIR bool constants so make sure to handle that.

Add test for object model IR with bool constants.
2024-08-05 12:21:19 -05:00
Fabian Schuiki cbdee94d96
[Support] Add FVInt, a four-valued arbitrary precision integer (#7422)
Add the `FVInt` class to CIRCT's support library. This class can
represent arbitrary precision integers where each bit can be one of the
four values 0, 1, X, and Z. The name intends to suggest a *four-valued
APInt*, with the option to also introduce a *nine-valued NVInt* in the
future.

Internally, `FVInt` uses two `APInt`s to store its data: `value` stores
whether a bit is 0/X or 1/Z, and `unknown` stores whether a bit is known
(0 or 1) or unknown (X or Z). Together they allocate 2 bits of storage
for each of the `FVInt`'s digits, which allows for four different values
per digit. This representation as `value` and `unknown` makes many of
the logical and arithmetic operations pretty straightforward to
implement. Most four-valued operations can be trivially implemented by
performing the equivalent two-valued operation on `value`, and then
accounting for X and Z bits through a few logic operations on `unknown`.

Note that Slang defines its own version of this (`SVInt`). But since
Slang is an optional dependency of CIRCT, it makes sense to have a CIRCT
equivalent that is built around LLVM's `APInt`, for use in our dialects.

This first version of `FVInt` has a rather incomplete set of operations,
but it covers basic AND, OR, XOR, NOT, negation, addition, subtraction,
and multiplication as a proof-of-concept. The remaining operations will
be added in future commits. We are also going to need a four-valued
equivalent of `IntegerAttr` based on `FVInt`.

This commit is motivated by the Slang frontend, which now supports
enough of SystemVerilog to make some test designs start to hit the lack
of number literals with X and Z.
2024-08-05 09:42:26 -07:00
Hideto Ueno 461c63146e
[FIRRTL][LowerDPI] Lower FIRRTL vector to an open array type (#7305)
Previously a FIRRTL vector was lowered into a packed array and there was no way
to generate an open array. This PR changes to use unpacked open array which is
supported by several tools (at least verilator and vcs) by default.
2024-08-05 12:21:05 +09:00
Fabian Schuiki 7df593d081
[ImportVerilog] Fix value domain mismatch for logic/ternary ops
Fix an issue in the mapping of the logical `&&`, `||`, `->`, and `<->`
operators, where the left and right-hand side could have different value
domains in the AST (one `logic`, one `bit`).

Similarly, fix an issue with the `?:` ternary operator where the true
and false expressions could have different but cast-compatible types.
2024-08-04 12:33:37 -07:00
Schuyler Eldridge c26d7705c3
[OM] Add IntegerAttr -> Python int conversion (#7430)
Add a missing conversion for OM to Python conversion where only OM
integers and not arbitrary MLIR integers would be converted to Python.
This could result in failures in Python scripts that needed to consume OM.

This fixes a bug introduced in: 17c036f87c

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2024-08-04 14:03:21 -04:00
Fabian Schuiki e95e92dd19
[ImportVerilog] Add rvalue assignment pattern support (#7428)
Add support for assignment patterns like `'{42, 9001}` in rvalue
position. These are roughly SystemVerilog's equivalent of
`struct_create` and `array_create`. This commit also adds an
`array_create` op to support assignment patterns for arrays.
2024-08-04 11:01:00 -07:00
elhewaty 17e85f15c7
[Arc] Make the canonicalizer shuffle the input vector elements before merging (#7394) 2024-08-03 22:51:13 -07:00
elhewaty 17545bc101
[Arc] Fix crash in the arc canonicalizer produced by the KeepOneVecOp optimization (#7429) 2024-08-03 21:07:03 +03:00
Fabian Schuiki 6eda5a2b5e
[circt-verilog] Fix lint only mode, refactor pass population
If circt-verilog is run in lint-only mode, actually make the tool exit
out after the initial parsing through Slang. All diagnostics have been
reported at that point, and we can just exit out without bothering with
any IR modifications.

Also refactor the way circt-verilog populates its pass pipeline a bit.
2024-08-03 10:14:59 -07:00
Will Dietz f470dac1ed
[FIRRTL][Dedup] Improve diagnostic for failing to dedup due to public. (#7426) 2024-08-02 13:40:14 -05:00
Fabian Schuiki 58f6daa425
[ImportVerilog] Ignore type parameters
Ignore type parameter AST nodes since these are already handled during
Slang's type checking pass. Also tweak the diagnostics on unsupported
SV constructs to be a bit more descriptive.
2024-08-02 11:37:43 -07:00
Fabian Schuiki 272af6c158
[ImportVerilog] Add missing conversions, various fixes
Add missing conversions for cases where the Slang AST has expressions
operating directly on packed structs/arrays, but the Moore IR expects
a conversion to a simple bit vector type.

Also clean up a few things and remove an invalid `struct_inject`
conversion.
2024-08-02 11:37:43 -07:00
Will Dietz 20cb546d18
[FIRRTL][Dedup] Rework hashing for perf and bug fixes. (#7420)
Primary change is to only generate and populate mappings for
sources of values, and not each value themselves.

Values are identified using these base numberings plus an appropriate
offset.

The main benefit of this is to greatly reduce the number of entries in the
`indices` map.
When handling operations with many block arguments (module-like's with many
ports) or with many results (instances of those module-like's) this greatly
reduces the pressure on the `indices` map.  For these designs, dedup now runs
dramatically faster and uses significantly less memory.

Also separates location of the value impl, such that if a Value's impl is storage
inline into an Operation or Block such that there is aliasing, the two
are given different numbers (and especially the numbering isn't changed).

On a synthetic design containing a module with 2^20 ports and 256 instances of
that module, this is the difference between completing in 20s and OOM'ing on my
machine after running for 30 minutes.

Functional changes:

Fixes #7415.
Fixes #7416.
Also fixes deduping if block arg types are different (but unused).

This is done by hashing block count, and each block's numbering between
as well as the types of its arguments before that block's operations.

Additionally fixes use of numberings (indices) before it was
populated where attribute processing for inner symbol ports
hashed using the block argument's numbering before it was populated.
2024-08-01 07:02:53 -05:00
Bea Healy 2dbab26c89
[docs] Remove confusing reset in Seq docs SV example (#7419) 2024-08-01 10:06:29 +01:00
Mike Urbach 17c036f87c
[OM] Pass Python values back and forth, not Attributes. (#7417)
Internally, primitive OM EvaluatorValues are represented as
TypedAttributes. This is great internally, but when we pass these from
C++ out to Python, we have to use a very inefficient method to pull
the Python value out of the attribute.

This updates how primitives are handled at the Python <> C++ interface
to directly construct the appropriate Python values and return
them. Similarly, for top-level inputs to the Evaluator, Python values
are directly accepted and converted to Attributes internally.

On large designs, this was shown to decrease single threaded CPU time
to process large amounts of OM data by roughly 70%. There is no
difference in the output.
2024-07-31 12:19:12 -06:00
Jiahan Xie 3c12682a1a
Support `scf.if` Op Lowering to Calyx (#6256)
* support lowering scf if op and add a corresponding test
2024-07-31 11:47:59 -04:00
John Demme 05136f0cac
[ESI] MMIO: add read/write port so service (#7407)
Replaces write with read_write.
2024-07-31 05:42:57 -07:00
wenhu1024 41841ebb86
[ImportVerilog] Support for String Types, String Literals (#7403)
Co-authored-by: itaras20 <ian.taras20@gmail.com>
2024-07-31 13:52:11 +08:00
Andrew Young 7ef41080ac [FIRRTL] SpecializeLayers: support default specialization mode
This modifies the SpecializeLayers pass to understand the default layer
specialization mode specified on a circuit.
2024-07-30 13:43:29 -07:00
Andrew Young 856a4e6c06 [firtool] Add option to specify default layer specialization mode
This adds a command line option to specify the default layer
specialization mode.
2024-07-30 13:43:29 -07:00
Andrew Young b4e85d6409 [FIRRTL] Add default layer specialization mode to CircuitOp
This adds a default layer specialization mode attribute to the FIRRTL
CircuitOp.  This will be used by the layer specialization pass to
specialize layers that were not explitly enabled or disabled.
2024-07-30 13:43:29 -07:00
Andrew Young 2323d2d285 [FIRRTL] Add LayerSpecialization attribute
This adds a new LayerSpecialization attribute, which will eventually be
used to specify the default mode of specialization on a circuit.
2024-07-30 13:43:29 -07:00
Julian Oppermann ca2c7dc587
[Scheduling] Replace macro use in problem definitions (#7320) 2024-07-30 22:23:43 +02:00
Fabian Schuiki b7b82fda8b
[Moore] Clean up struct ops and add missing tests (#7392)
Rework the Moore dialect operations that manipulate struct values. These
are intended to operate on `StructType` and `UnpackedStructType` values
directly, but were defined in ODS as operating on references to structs.
This was likely a hold-over from early development where we were still
figuring out the distinction between ref types and value types in SV.

This commit adjusts the struct ops such that they actually operate on
struct values instead of references to structs. It also moves more
operand constraints into ODS and simplifies the op verifiers by
factoring out some common code into helper functions.

Enhance the `struct_inject` canonicalizer to also consider
`struct_create` operations as part of the inject chain. This allows an
initial `struct_create` that is modified by a subsequent inject to be
canonicalized into a new `struct_create` with updated values.

Add missing basic and error tests for the struct-related ops, and
simplify the variable destructuring test by removing unrelated
operations.

Also fixes an issue in variable op destructuring where a variable with
initial value would have its initial value discarded during
destructuring. Initial values now prevent destructuring. Alternatively,
we may choose to insert appropriate `struct_extract` ops to destructure
the initial value in the future.
2024-07-30 12:26:08 -07:00
Hideto Ueno 68b568b68e
[PrepareForEmission] Hoist registers in a procedural region with `disallowLocalVariables` (#7404)
Fix https://github.com/llvm/circt/issues/7399
2024-07-31 00:20:53 +09:00
Amelia Dobis 15417e841e
[Verif] Introduce Formal Contracts (#7325)
This PR proposes a new set of ops aimed at enabling the use of formal contracts to abstract away module instances during verification.

There is still some work needed to handle these ops in PrepareForFormal, which will be done in a later PR.
2024-07-29 15:24:43 -07:00