* [mooretocore] Support namedconstant
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
* Limit type to integertype.
* add mooretocore support
* remove include
* remove verify of hwops
* remove include
* Test added.
* Add test for MooreToCore
* Support any attribute
* Modify test.
* Add symbol for wireOp
* Remove useless include
* Add more test and error cases
* slang-tidy
* some Imporvement
* Improved version
* little change
* Imporve
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Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
Add a new CombDataflow op interface to FIRRTL.
This interface is used for specifying the combinational dataflow that exists in
the results and operands of an operation. Any operation that doesn't implement
this interface is assumed to have a combinational dependence from each operand
to each result.
Currently only FIRRTL register and memory ops implement this interface, but it
can be used in other dialects that intend to use the CheckCombCycles pass.
This PR modifies ExportVerilog to emit two state types (`bit` in general) for DPI import op. Furthermore, for specific bit width (8, 16, 32 and 64) it emits C-types (byte, shortint, int and longint).
This PR also rejects small integer types other than 8, 16, 32 and 64 bit width since otherwise we have to use`bit` but they are passed by references in DPI. So this PR defines the ABI as "small integers are passed by values, and larger integers are passed by references.
This PR adds DPICallIntrinsicOp and its lowering pass. DPICallIntrinsicOp is lowered into sim.func.dpi.call and sim.func.dpi ops. At FIRRTL level DPICallIntrinsicOp doesn't have symbols and instead LowerDPI pass accumulates call sites and creates symbols for dpi functions. LowerDPI pass directly lowers FIRRTL intrinsic into Sim dialect since FIRRTL doesn't have DPI/Function construct. LowerDPI pass could be simplified (or migrated into LowerToHW) once FIRRTL gets 1st class support for Function. Unrealized conversion cast is used to mix FIRRTL and HW type values before LowerToHW.
ODS InterfacePass generates `canScheduleOn` method with a specified interface in a header file and currently we import every pass declaration through PassesDetail.h. Gcc/clang seem to compile when there is an unknown interface class but MSVC emits an error. So this PR avoids `InterfacePass` in ODS and manually implements `canScheduleOn` in PrepareForEmission.
This PR adds DPI func/call op and SimToSV lowering.
`sim.dpi.func` is a just bridge to `sv.func`. This op can be lowered into `func.func` in the future for Arc integration.
`sim.func.dpi.call` represents SystemVerilog DPI function call. There are two optional operands `clock` and `enable`.
If `clock` is not provided, the callee is invoked when input values are changed. If provided, the dpi function is called at clock's posedge. The result values behave like registers and the DPI function is used as a state transfer function of them. `enable` operand is used to conditionally call the DPI since DPI call could be quite more expensive than native constructs. When `enable` is low, results of unclocked calls are undefined and in SV results they are lowered into `X`. Users are expected to gate result values by another `enable` to model a default value of results. For clocked calls, a low enable means that its register state transfer function is not called. Hence their values will not be modify in that clock.
A function that returns an explicit return is not supported yet.
This commit adds the DUT module instance path to the to the `SiFive_Metadata`
class. This is required to generate the DUT instance path directly from the
OMIR. This will be required to generate DUT relative hierarchy paths for
memories in the seq_mems.json metadata, Since all paths are by default
generated relative to the top level.
This commit creates a list of paths, to handle multiple DUTs even though the
current designs will have a unique DUT.
Bump minimum supported FIRRTL to 2.0.0.
"FIRRTL version" is now required as a result.
Remove parsing of the FIRRTL partial connect operator ("<-"). This has,
for a very long time, been almost unreachable from Chisel-emitted FIRRTL
and is now impossible to emit from Chisel. This has also been completely
removed from the FIRRTL spec in version 2.0.0.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Taps (using probes) support a non-passive source with a passive sink (by their nature), but the hidden option to avoid probes does not.
Detect this specifically and fix by using passive type for wiring from source.
This allows taps of non-ground (non-passive) that work with probes to also work with this option.
* [MooreToCore] Add conversion support for SVModuleOp and InstanceOp
* Trailing newline fix
* Add Fixme
* [MooreToCore] Add a new test case for svmoduleOp and instanceOp
This is a rather crude version without assignOp, variableOp and netOp in the examples.
We generally type-erase objects at the boundary, to avoid needing to
declare the objects' classes as part of the interface. This adds a
cast for the metadataObj reference, so we don't have to declare its
class as part of the interface. The evaluator and any tooling built on
it already know how to "see through" this cast.
... while factoring out `InnerSymbol`+name logic into a new interface that is also used by Ibis port-like ops. This model could probably be factored into the `hw` dialect, seeing as we're also eventually going to divorce symbol names and actual names in `hw.module`.
Also adds de-aliasing logic to `ContainersToHW`, which is required given that `hw.module` doesn't yet split its symbol and name (#7023).
This PR implements ExportVerilog support of sv.func, sv.func.dpi.import, sv.func.call and sv.func.call.procedural.
sv.func emission is similar to hw.module but one difference is a return value. Surprisingly in SV a function name is used as a placeholder for a return value so name legalization properly sets `hw.verilogName` of a returned value to a function name.
Result names of sv.func.call.procedural are attached to temporary registers created in PrepareForEmission. This is similar implementation approach to hw.instance.
[Moore] Modify the tests related to the RefType.
Add a wrapper type(moore::RefType) to work for VariableOp/NetOp, ReadOp, and AssignOpBase, and it can wrap any SystemVerilog types. We added RefType in order to introduce Mem2Reg into moore to eliminate the local temporary variables. Meanwhile, we added a new op named moore.extract_ref which is the copy of moore.extract that explicitly works on the ref type. And moore.concat_ref is the copy of moore.concat. Later, we will tweak union/struct ops like moore.struct_create in order to support the ref type.
moore.variable/moore.net will return a result with ref<T>, it's similar to memref.alloca.
Change moore::ReadLValueOp to moore::ReadOp, it's similar to memref.load. Initially, we need moore.read_lvalue only to service for assigmen operations(like +=, *=, etc). However, moore. read is not only for assignment operations but also to take a value with RefType(ref) and return the current value with the nested type(T). For example, a = b + c, moore.read will take b and c(both are ref<T>), and then return a value with the nested type(T).
We think the MooreLValueType and VariableDeclOp(52a71a6) that had been removed eventually found their proper site.
We also divide convertExpression() into convertLvalueExpression() for the LHS of assignments and convertRvalueExpression() for the RHS of assignments. The former will return a value with RefType like ref<i32>, but the latter returns a value without RefType like i32.
Co-authored-by: Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
This changes pre-passes for ExportVerilog to run on HWEmittableModuleLike instead of HWModuleOp. #6977 is going to add a support for SV func op and legalization needed for SV func as well.
HWEmittableModuleLike is a new interface that inherits Emittable+HWModuleLike. I considered to use a trait but we cannot use a trait for pass scheduling so an interface is used.