This is quite invasive. This converts from the functiontype printer to the moduletype printer.
---------
Co-authored-by: Mike Urbach <mikeurbach@gmail.com>
* [Conversions][Transforms] Add missing includes due to refactoring in upstream MLIR.
LLVM commit 36d3efea15e6202edd64b05de38d8379e2baddb2 removed a few
include statements from mlir/Pass/Pass.h, so we have to update a few of
the files here to add back in some includes.
* [Handshake][SV] Migrate from StrEnumAttr to EnumAttr.
StrEnumAttr was removed in upstream LLVM commit
60e34f8dddb4a3ae5b82e8d55728c021126c4af8. It has been replaced with
EnumAttr, which can do everything that StrEnumAttr could do but more
efficiently.
This affected two specific attributes: Handshake's BufferType, and SV's
ModportDirectionAttr. Both have been converted over to EnumAttrs. Their
parsers had to be updated, since the new EnumAttr no longer likes having
double quotes around the enum value in the assembly format.
Consequently, the tests were also updated.
* Bump llvm to 1aa4f0bb6cc21b7666718f5534c88d03152ddfb1.
* Add a File Descriptor parameter to FWriteOp
`sv.fwrite` now accepts an i32 argument pointing to an arbitrary file descriptor.
```
%0 = hw.constant 0x80000002
fwrite %0, "write to stderr"
```
resolvesllvm/circt#2062
This may fix#2176:
These are logically equivalent operations. array_slice should use the same syntax (but have the additional return type).
I think this issue is proposing changing array_slice syntax to use square bracket?
I did some small change to td file, but not so sure if this is the syntax that @lattner originally want.
Additionally, I also have a question about the type assembly format for hw.array_slice and hw.array_get:
hw.array_slice serialize the input parameter type, while hw.array_get doesn't. I thought types of ODS format should always be explicit, while this seems to be a counter example. Just curious the originally design purpose here.
Co-authored-by: Andrew Lenharth <andrew@lenharth.org>
A temporary fix for integration tests, to disable verilator width warning.
As a followup we need to respect `disallowPackedArrays `
to not generate packed arrays and lower them accordingly.
Verilog exporting was moved from a translation to a proper pass. As a
part of this change, it should be invoked by `circt-opt` instead of
`circt-translate`. This change should fix the integration build.
Removes the result type from the comb.concat type signature since it can be
deduced from the inputs.
For example, this previous signature:
```mlir
%0 = comb.concat %false, %b : (i1, i4) -> i5
```
is simplified to:
```mlir
%0 = comb.concat %false, %b : i1, i4
```
Address #1623.
`equiv-rtl.sh` is a utility script used to test formal equivalence in
our integration tests. This change adds it as a tool which Lit knows
how to find instead of using a relative path to invoke the script.
This test is probably too narrow to be part of the integration test
suite. It ensures the tool does what we expect, with the constructs we
emit from ExportVerilog. Closes
https://github.com/llvm/circt/issues/1368.
This makes sure not to rename FIRRTL to HWRTL :-), and I spot checked a
many things to avoid changing general references to RTL (e.g. when referring
to external tools) but I suspect that I missed some. Please let me know (or
directly correct) any mistakes in this mechanical patch.
* Update the golden verilog with the latest firrtl
* firrtl output for neg, for signed and unsigned operand must respect the sign.
* This should fix the yosys integration_test failure https://github.com/llvm/circt/issues/842
* The firrtl bug fix that updates the golden: 49b8232447
- The ESI export verilog test is too fragile. Making more resilient to
ExportVerilog changes.
- Missed some bitcast dialog changes in the integration tests
* Move comb.constant to rtl
* add missing
* fix
* fix ExportVerilog and example
* format
* format
* remove unnecessary header
* materialize constant
* format
* rebase
* fix
* clang-format
Rename the "reduction Xor" operator to "Parity" in Comb dialect.
Semantics remain exactly same and export verilog also doesnot change.
Discussed in: https://github.com/llvm/circt/issues/598
* Remove comb.OrROp and replace with == -1
Remove "reduction and" from the comb dialect, and instead use "== -1".
Update lowering from FIRRTL to use "== -1"
Also update verilog export to emit "&" whenever "==-1" is encountered.
Remove the specific tests for "and or ", like the folding and canonicalization ones.
Add tests for FIRRTL lowering and Verilog emitting
This change changes all command line options to use the import and
export nomenclature as described in the MLIR glossary[0]. This is a
a continuation of the renaming work which occured in #341.
[0] https://mlir.llvm.org/getting_started/Glossary/
The MLIR printer has been modified to print enumerations without quotes
when they are not needed. This provides a nice upgrade to readability.
```mlir
// from:
%1 = cmpi "slt", %0, %c42 : index
// to:
%1 = cmpi slt, %0, %c42 : index
```
* Cast(To|From)Bits
* ExportVerilog support
* No valid cast syntax which I could find
* Adding support for structs
* I think this is everything except for the documentation.
* Changing back unrelated, spurious comment formatting
* Fixing test
* Specify bit layout of types
* Incorporating Chris' feedback
John Demme