Commit Graph

8551 Commits

Author SHA1 Message Date
Hideto Ueno bd259e788a
[SV] Add sv.func, sv.return and sv.func.call operations (#7003)
This PR adds function call constructs (sv.func, sv.return and sv.func.call) to SV dialect. 

* `sv.func` -- this op is between hw.module and func.func. This op implement interfaces `PortList`, `HWModuleLike` and `FunctionOpInterface`. Similar to hw.module, we can preserve argument names and mix the order of input and output arguments. Following func.func empty body indicates that the op is a declaration. Currently sv/func is defined as "automatic" function in SV.
* `sv.return` -- terminator for sv.func. We cannot reuse neither hw.output nor func.func since they have constraints on parent op(and I think it's not reasonable to loose them). 
* `sv.func.call` and `sv.func.call.procedural`. Two operations are added because output arguments cannot be used non-procedural regions.
2024-05-16 16:52:38 +09:00
John Demme b64af242f2
[ESI][Cosim][NFC] Refactor cosim to divorce capnp from DPI (#7045)
Move generic functionality into Capnp library. This divorces it from the
DPI server, allowing other things to use it. Additionally, divorce
server from general functionality to make adding a client thread easier.
2024-05-15 18:18:24 -07:00
Will Dietz 6e028d64bd
[FIRRTL][Intrinsics] source materialization for inferred types. (#7043)
If the new op's result doesn't match, insert a wire + connect
(if valid) to handle the mismatch.

For intrinsics that lower to ops with return type inference,
the inferred type may be different than the declared type
(e.g., `UInt` vs `UInt<1>`).
2024-05-15 14:32:21 -05:00
Fabian Schuiki 9cbb45552a
[Moore] Move IntType definition into ODS (#7035)
Replace the C++ definition of `IntType` with a corresponding table-gen
definition in `MooreTypes.td`.
2024-05-15 11:11:39 -07:00
Bea Healy cb61e8fd9f
[Arc] Add SplitFuncsPass (#7027)
Adds a pass to split up large functions in Arcilator.

---------

Co-authored-by: Martin Erhart <maerhart@outlook.com>
2024-05-15 18:03:38 +01:00
Will Dietz ba597c63da
[FIRRTL][NFC] Replace intmodules with intrinsic expressions in test. (#7041) 2024-05-15 11:05:35 -05:00
Andrew Lenharth 0a18183fa0 [NFC] silence warning 2024-05-15 08:56:37 -07:00
Martin Erhart 481cb60add
[CombToSMT] Make result of div-by-zero undefined (#7025)
This adapts the conversion pass to match the recently agreed upon definition for division by zero. Integration tests for circt-lec are added to check the behavior. Note that two syntactically equivalent modules are not considered equivalent if they aren't guaranteed to deterministically produce the same outputs. Alternatively, we could consider two undefined output values equivalent by modeling each value as a pair of a boolean and the bit-vector where the boolean determines if the value is undefined, then two outputs are equivalent if either the boolean is true or the boolean is false and the bitvectors match. There are probably use-cases for both, so maybe we'd want a flag to let the user decide.
2024-05-14 08:09:34 +02:00
John Demme b51a6448d0
[ESI][Runtime] Don't pull down JSON dependency if already defined
Since nlohmann_json is a pretty common dependency, if that target already exists, don't re-download it and run its CMakeLists. This is helpful when the ESI runtime is being itself fetched through cmake `FetchContent`.
2024-05-13 20:07:25 -07:00
John Demme f1a822e597
[SV] Add `sv.reserve_names` op to disallow names (#7024)
Introduce an op to specific a list of names which Export Verilog should never use anywhere. Applies to module names, port names, reg/wire/logic names, etc.
2024-05-13 19:53:26 -07:00
Hideto Ueno 6fb270b319
[OM] Separate OM object fields verifier to a dedicated pass (#7026)
Verification for OM object fields performs global analysis on a symbol table op. This cannot be done efficiently today within symbol table verification without nested symbol tables. So this PR separates the verifier into a dedicated pass and run the verification at several times in the pipeline.
2024-05-14 11:24:02 +09:00
John Demme c3fd7f1a6b
[ESI][Runtime] Remove C++ includes from wheels (#7032)
There is no good way to use the binaries included with the wheel.
Essentially, they are built with the old `std::basic_string` but modern
software uses `std::__cxx11::basic_string`. There is now way to change
this behavior (AFAICT) in manylinux2014. Newer manylinux images have a
way, but we need compatiblity back to glibc 2.17, which none of them
provide.
2024-05-13 18:59:28 -07:00
Will Dietz e117ac3a0b
cmake: circt install directory for CAPI (#7028) 2024-05-13 19:10:34 -05:00
John Demme 474fc3f4a4
[ESI][Runtime] Python wheel now provides cpp support (#7001)
Wheel install now contains C++ headers, cmake file, and python func for
cmake location.
2024-05-13 14:02:20 -07:00
Hideto Ueno 4a240b9f50
[OM] Add IsolatedFromAbove to OMClass (#7020)
This adds IsolatedFromAbove to OMClassOp and OMClassExternOp. It should make local verification run parallelly.
2024-05-13 15:39:28 +09:00
Amelia Dobis 684262ac23
[FIRRTL] Add condition expansion for ExpandWhens on Property intrinsics (#7021)
* Added when expansion to Property intrinsics

* clang-tidy

* Update test/Dialect/FIRRTL/expand-whens.mlir

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

---------

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
2024-05-10 17:05:52 -07:00
Amelia Dobis c09a0ff163
[docs] Updated example test in GettingStarted.md 2024-05-10 09:59:39 -07:00
Amelia Dobis 0d120ca486
[docs] Add basic pass tutorial (#7012)
* Added small pass tutorial in getting started docs

* Added small pass tutorial in getting started docs

* Added basic pass tutorial

* Cleaned up pass in getting started doc and added links to better tutorials

* added tutorial pass

* fixed missing imports

* added a test

* added links to tutorial files

* udpated target flags

* nl@eof

* Update GettingStarted.md

* fixed typo in flags
2024-05-10 09:43:49 -07:00
Prithayan Barua bc5ef52459
[AddSeqMemPorts] Add hierpathop to verbatim, instead of raw instance path (#7014)
The annotation `AddSeqMemPortsFileAnnotation` causes the pass
 `AddSeqMemPort` to add verbatim ops for the SRAM metadata file.
The file lists each SRAM and provides the mapping to
where it is in the hierarchy, and gives its IO prefix at the DUT top level.

This PR updates the pass to use `HierPathOp` to print the SRAM instance path,
 instead of the raw list of symbol references. 
This is required to ensure that the instance path is valid, even if the hierarchy
is updated by following passes.

This fixes a `firtool` crash that is exposed when using `AddSeqMem` along with
 `ExtractSeqMem`. Which is due to invalid symbol references in the `varbatim`, after
 the hierarchy was updated. Even though, this particular use case is invalid, as these
 two SRAM annotations cannot be used together, it can still be triggered by other
transformations.

Note: This metadata will soon be moved to OM, in a followup PR.
2024-05-10 08:44:16 -07:00
Fabian Schuiki 6a2b628129
[Moore] Make simple bit vectors a proper MLIR type (#7011)
The core type most SystemVerilog expressions are interested in and
operate on is a "simple bit vector type". These are individual integer
atoms like `bit` or `logic`, integral types like `int`, or packed arrays
with a single dimension and an integer atom inner type, like
`bit [42:0]`. So in a nutshell, simple bit vector types are MLIR's `i42`
in the two-valued (`bit`) case, or the four-valued equivalent (`logic`).

Up until this point, the Moore dialect reflected this pattern by
providing and `IntType` for the integer atoms like `bit` and `int`, and
using the `PackedRangeDim` for single dimension vectors of `bit`. A
`SimpleBitVectorType` helper struct would then summarize the _actual_
bit vector that was expressed by the packed range and integer atom. This
makes working with the types in TableGen files very annoying, since the
thing you are actually interested in -- the simple bit vector -- is not
a propery MLIR type, but more like a helper struct on the side.

This commit rips out the existing `IntType` and its composition with a
packed array dimension, and replaces it with a proper simple bit vector
type that is actually an MLIR type. As a result, SystemVerilog types
like `int unsigned`, `bit [42:0]`, `reg`, `logic signed [31:0]`, or
`integer` are all translated into the same MLIR type. This new simple
bit vector MLIR type retains the `IntType` name, and prints as
`!moore.i42` or `!moore.l42`, depending on whether it is a two-valued or
four-valued integer. Single `bit` and `logic` atoms become `i1` and `l1`
respectively.

This makes the Moore type system a lot easier to work with and removes
a lot of unnecessary noise. Operations can now simply use
`llvm::isa<IntType>` to check if a value is a simple bit vector.
2024-05-09 15:52:20 -07:00
devins2518 5ac765214c
[ARC][CAPI] Add basic C API for initializing ARC (#6997) 2024-05-09 15:48:12 -07:00
fzi-hielscher 98db979403
[HWToSMT][circt-lec] Resolve transitive !smt.bool -> i1 -> !smt.bv<1> casts. (#7006) 2024-05-09 23:36:42 +02:00
Amelia Dobis 12c44ada53
[docs] Add cmake flags that reduce memory usage (#7018)
* Added small pass tutorial in getting started docs

* Added small pass tutorial in getting started docs

* Added basic pass tutorial

* added cmake flags to reducs memory usage

* added cmake flags to reduce memory usage

* comments
2024-05-09 14:26:21 -07:00
Fabian Schuiki 719bbfde79
[CAPI] Add circt-capi target and build it in CI (#7017)
Add a `circt-capi` target that depends on all C API libraries. Introduce
a new `add_circt_public_c_api_library` CMake function that wraps around
the MLIR equivalent, but also adds a dependency from `circt-capi`. Make
at least the short integration tests CI job build the `circt-capi`
target to ensure it has a bit of CI coverage.
2024-05-09 11:21:33 -07:00
Fabian Schuiki 1a311bbc32
[CAPI][Moore] Remove signedness
Update the Moore C API to match changes made to the type system. CI
doesn't build the C API currently, which means these breakages often go
unnoticed.
2024-05-09 10:35:14 -07:00
Will Dietz 3008f9cedb [FIRRTL][Dedup][NFC] Remove check for input probes.
These are verified to not exist, don't bother checking for them.
2024-05-09 12:29:30 -05:00
Will Dietz 0861eef6e6
[FIRRTL] Don't prefix an empty label for unclocked assume. (#7016)
Add FIR -> SV test for "unclocked_assert" since we care about ensuring
it has a specific shape re:output.

Test extracted from #7010.
2024-05-09 12:18:46 -05:00
Will Dietz d1b4259621
[FIRRTL] Make input probes illegal (#6921)
Disallow input probes.
cc chipsalliance/firrtl-spec#183 .

Adds verifier for this, and mostly updates tests.

Delete ProbeDCE.

Many passes can (and should) be simplified as they do not need to consider this any longer.
2024-05-09 10:39:58 -05:00
hovind d913a5adb0
[HW][LegalizeModules] Avoid segmentation fault (#7013) 2024-05-09 19:47:02 +09:00
Amelia Dobis 7073e2cfdc
LLVM Bump (#6993)
* llvm-bump

* llvm-bump (again)

* [FIRRTL] AnnoTarget: use LLVM style casts (#7007)

This changes AnnoTargets to use LLVM style casts instead of "trailing"
member functions. The LLVM style casts are now usable with AnnoTargets
with improvements to the upstream framework.  The current style of cast
used with AnnoTargets will no longer be supported by TypeSwitch, so this
PR switches to the recommended idiom.

Authored-by: Andrew Young <youngar17@gmail.com>

* updated cast uses
2024-05-08 17:42:07 -07:00
Andrew Young 4f4ead0a5e
[FIRRTL] AnnoTarget: use LLVM style casts (#7002)
This changes AnnoTargets to use LLVM style casts instead of "trailing"
member functions. The LLVM style casts are now usable with AnnoTargets
with improvements to the upstream framework.  The current style of cast
used with AnnoTargets will no longer be supported by TypeSwitch, so this
change is needed to bump LLVM.
2024-05-08 16:48:26 -07:00
Fabian Schuiki 63c794f24e
[Moore] Move signedness from types into ops
Instead of annotating types as signed or unsigned, make Moore dialect
types signless and move the signedness into operations. This affects
division, modulus/remainder, and comparison operations. These now come
in a signed and unsigned flavor. ImportVerilog consults the Slang AST
type to determine signedness when creating Moore dialect ops. The Moore
types themselves now no longer carry any sign information. This
significantly simplifies the dialect and takes the type system one step
closer towards having just a basic two- and four-valued bit vector type.
2024-05-08 15:52:10 -07:00
Will Dietz 54ace0c344
[FIRRTL][LowerIntrinsics] Add stat and preserve if no changes. (#6911) 2024-05-08 17:05:00 -05:00
Will Dietz c18a7c4646
[FIRRTL][NFC] Drop use of intmodule's in tests. (#7008) 2024-05-08 16:32:32 -05:00
Amelia Dobis 57c0764f85
[firtool] Add FlattenModulesPass to the btor2 emission pipeline (#6999)
* Added FlattenModulesPass to the btor2 emission pipeline

* added pass registration

* cleaned up pass registration
2024-05-07 23:10:19 -07:00
Hailong Sun 06cb84a83e
[ImportVerilog] Fix unknown name caused by local variables. (#6995) 2024-05-08 09:53:24 +08:00
Fabian Schuiki 9db5bc8167
[Moore] Remove formatting of types as SV string
Remove the `format` functions from the types in the Moore dialect. These
could format a type as SystemVerilog syntax to a certain extent, but
they are unused in practice. The formatting was useful in the original
Rust implementation to produce nice error messages during type checking.
Since Slang performs type checking for us, the formatting is no longer
needed.
2024-05-07 18:14:20 -07:00
John Demme 7cd0ea9bc6
[pycde] Disallow structs with zero fields (#7000)
Also, fix IbisClass for functions with zero arguments.

Co-authored-by: Morten Borup Petersen <morten_bp@live.dk>
2024-05-07 17:45:04 -07:00
Fabian Schuiki ac66ece240 [Moore] Remove name and location from struct type
Remove the name and location info from struct types in the Moore
dialect. This simplifies the assembly syntax and removes unused
information.
2024-05-07 15:22:59 -07:00
Will Dietz db4f641b31
[FIRRTL][SFCCompat] Fix tests and handling of fullasyncreset on non-port. (#6984)
They are not limited to appearing on module ports.
Compute presence of full-async-reset accordingly,
and be sure to remove those annotations as well.

Fix various amounts of non-functional / vacuously passing tests.
2024-05-07 17:20:57 -05:00
fzi-hielscher 37d2891bbd
[NFC][clang-tidy] Disallow global 'using' directives in headers (#6998)
Add the google-global-names-in-headers rule to the list of clang-tidy checks to prevent namespace pollution.

This is intended to flag global using-directives in header files during PR checks. Collisions between the llvm and the mlir namespace have caused obscure build failures on Windows in the past. #6844 should have removed all existing occurrences in the CIRCT code base.
2024-05-07 21:24:37 +02:00
Will Dietz b8fb074687
[FIRRTL][LowerAnnotations] Reject non-local fullasyncreset anno's. (#6988)
These are not understood in a non-local way, reject them.

Docs say this annotation cannot be used on a module instantiated
multiple times (apparently) so non-local should never be needed.
2024-05-07 09:32:29 -05:00
hovind 24b845cf3c
[CAPI][Moore] Remove deprecated types (#6994) 2024-05-07 12:00:41 +02:00
Martin Erhart 282bdb85b2 [Moore] Remove remaining usages of EnumType 2024-05-07 11:10:13 +02:00
Morten Borup Petersen aba85bf470
[Handshake] Add control_merge deconstruction pattern (#6934)
This pass deconstructs the (rather complex) semantics of a >2 input cmerge operation into a series of 2-input cmerge operations + supporting logic. This simpler structure is better suited for `dc` lowering, which only supports lowering 2-input control merge operations.

Simplify

fix test

Also split regular merges

nit

Fix index type propagation for cmerge

Also zext non-`builtin.index`-typed `control_merge` operations
2024-05-07 11:08:04 +02:00
Morten Borup Petersen 836e745b6b
[DC] Add merge lowering (#6943)
* [DC] Add merge lowering

Modelled after the Handshake lowering, however, becomes trivial with a 2-input merge.

* Add Handshake->DC merge lowerings

* Update lib/Conversion/DCToHW/DCToHW.cpp

Co-authored-by: Christian Ulmann <christianulmann@gmail.com>

* Update lib/Conversion/HandshakeToDC/HandshakeToDC.cpp

Co-authored-by: Christian Ulmann <christianulmann@gmail.com>

* format

* notifyMatchFailure

---------

Co-authored-by: Christian Ulmann <christianulmann@gmail.com>
2024-05-07 10:21:25 +02:00
Morten Borup Petersen 91348ba8f1
[Pipeline] Verify >0 result types for LatencyOp (#6992) 2024-05-07 09:56:51 +02:00
Fabian Schuiki 475c6b459c
[Moore] Remove named and ref types
Remove the named and ref types from the Moore dialect. These
corresponded to Verilog `typedef`s and the `type(<expr>)` syntax,
respectively. Since Slang performs full type checking on its AST, these
types are no longer necessary at the Moore dialect level. This
significantly simplifies the dialect's type system. Once we have a
working lowering from Slang to the core dialects, we can reintroduce a
dedicated type to track user-defined type names.
2024-05-06 21:09:45 -07:00
Fabian Schuiki a36c258349
[Moore] Remove enum type
Remove the enum type from the Moore dialect. No passes or lowerings
currently make use of this type, but imemdiately resolve it to its
underlying integer type instead. This simplifies the dialect. Once the
need for an enum type arises again in the future, we can define a new
one.
2024-05-06 20:45:34 -07:00
Fabian Schuiki 2769f6528a
[Moore] Move simple leaf types into TableGen; NFC
Move the definitions of the `void`, `string`, `chandle`, and `event`
types into TableGen.
2024-05-06 20:14:33 -07:00