[FIRRTL] Add AddSeqMemPorts Anno to LowerAnnotations (#3508)

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Andrew Young 2022-07-12 07:55:26 -07:00 committed by GitHub
parent cd138aba3b
commit fb6e84222b
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3 changed files with 11 additions and 3 deletions

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@ -183,6 +183,12 @@ constexpr const char *extractClockGatesAnnoClass =
constexpr const char *extractSeqMemsAnnoClass =
"sifive.enterprise.firrtl.ExtractSeqMemsFileAnnotation";
// AddSeqMemPort Annotations
constexpr const char *addSeqMemPortAnnoClass =
"sifive.enterprise.firrtl.AddSeqMemPortAnnotation";
constexpr const char *addSeqMemPortsFileAnnoClass =
"sifive.enterprise.firrtl.AddSeqMemPortsFileAnnotation";
} // namespace firrtl
} // namespace circt

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@ -145,11 +145,11 @@ LogicalResult AddSeqMemPortsPass::processAnnos(CircuitOp circuit) {
AnnotationSet::removeAnnotations(circuit, [&](Annotation anno) {
if (error)
return false;
if (anno.isClass("sifive.enterprise.firrtl.AddSeqMemPortAnnotation")) {
if (anno.isClass(addSeqMemPortAnnoClass)) {
error = failed(processAddPortAnno(loc, anno));
return true;
}
if (anno.isClass("sifive.enterprise.firrtl.AddSeqMemPortsFileAnnotation")) {
if (anno.isClass(addSeqMemPortsFileAnnoClass)) {
error = failed(processFileAnno(loc, metadataDir, anno));
return true;
}

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@ -384,7 +384,9 @@ static const llvm::StringMap<AnnoRecord> annotationRecords{{
{extractCoverageAnnoClass, NoTargetAnnotation},
{dftTestModeEnableAnnoClass, {stdResolve, applyWithoutTarget<true>}},
{runFIRRTLTransformAnnoClass, {noResolve, drop}},
{mustDedupAnnoClass, NoTargetAnnotation}
{mustDedupAnnoClass, NoTargetAnnotation},
{addSeqMemPortAnnoClass, NoTargetAnnotation},
{addSeqMemPortsFileAnnoClass, NoTargetAnnotation}
}};