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[FIRRTL] Add AddSeqMemPorts Anno to LowerAnnotations (#3508)
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@ -183,6 +183,12 @@ constexpr const char *extractClockGatesAnnoClass =
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constexpr const char *extractSeqMemsAnnoClass =
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"sifive.enterprise.firrtl.ExtractSeqMemsFileAnnotation";
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// AddSeqMemPort Annotations
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constexpr const char *addSeqMemPortAnnoClass =
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"sifive.enterprise.firrtl.AddSeqMemPortAnnotation";
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constexpr const char *addSeqMemPortsFileAnnoClass =
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"sifive.enterprise.firrtl.AddSeqMemPortsFileAnnotation";
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} // namespace firrtl
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} // namespace circt
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@ -145,11 +145,11 @@ LogicalResult AddSeqMemPortsPass::processAnnos(CircuitOp circuit) {
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AnnotationSet::removeAnnotations(circuit, [&](Annotation anno) {
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if (error)
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return false;
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if (anno.isClass("sifive.enterprise.firrtl.AddSeqMemPortAnnotation")) {
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if (anno.isClass(addSeqMemPortAnnoClass)) {
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error = failed(processAddPortAnno(loc, anno));
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return true;
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}
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if (anno.isClass("sifive.enterprise.firrtl.AddSeqMemPortsFileAnnotation")) {
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if (anno.isClass(addSeqMemPortsFileAnnoClass)) {
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error = failed(processFileAnno(loc, metadataDir, anno));
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return true;
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}
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@ -384,7 +384,9 @@ static const llvm::StringMap<AnnoRecord> annotationRecords{{
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{extractCoverageAnnoClass, NoTargetAnnotation},
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{dftTestModeEnableAnnoClass, {stdResolve, applyWithoutTarget<true>}},
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{runFIRRTLTransformAnnoClass, {noResolve, drop}},
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{mustDedupAnnoClass, NoTargetAnnotation}
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{mustDedupAnnoClass, NoTargetAnnotation},
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{addSeqMemPortAnnoClass, NoTargetAnnotation},
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{addSeqMemPortsFileAnnoClass, NoTargetAnnotation}
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}};
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