mirror of https://github.com/llvm/circt.git
[Pipeline] Add non-stallable pipeline stages (#6018)
See rationale changes for an in-depth description of the why's and how's of this change.
This commit is contained in:
Morten Borup Petersen
GitHub
parent
8f4abacef5
commit
f3c9aa13ee
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@ -169,3 +169,64 @@ pipeline.stage ^bb4 regs(%out_s3 : i32)
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^bb4(%out_s4 : i32):
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foo.bar %out_s4 : i32
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```
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## Non-stallable Pipeline Stages
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**Note:** the following is only valid for pipelines with a stall signal.
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An option of the Pipeline abstraction presented in this dialect is the ability
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to have _non-stallable stages_ (NS). NS stages are used whereever a pipeline
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access resources that are not able to stop on a dime, and thus require a fixed
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amount of cycles to complete.
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Non-stallable stages are marked as an attribute of the pipeline operations,
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wherein a bitvector is provided (by the user) to indicate which stage(s) are
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non-stallable.
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To see how non-stallable stages are implemented, consider the following. For
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every stage, we define two signals - `S_{N,en}` is the signal that indicates
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that the stage currently has valid contents (i.e. not a bubble). `S_{N,valid}`
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is the signal that is used as a clock-enable for the output registers of a
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stage.
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Stages can be grouped into three distinct types based on how their valid signal
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is defined: stallable stages, non-stallable stages and runoff stages.
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<img title="Stage control" src="includes/img/Pipeline/stage_control.png"/>
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1. Stallable stages are any stages which appear **before** the first
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non-stallable stage in the pipeline.
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2. Non-stallable stages are the stages explicitly marked as non-stallable by the
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user.
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3. Runoff stages and stages that appear **after** (and by extension, **between**
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non-stallable stages). Runoff stages consider their own enablement wrt. the
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stall signal, as well as the enablement of the **last non-stallable
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register** (LNS) wrt. the runoff stage's position in the pipeline.
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The purpose of the runoff stages is to ensure that they are able to pass through
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as many pipeline cycles as there are upstream non-stallable stages, such that
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the contents of the non-stallable stages is not discarded.
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An important implication of this is that pipelines with non-stallable stages
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**must** be connected to some buffer mechanism that is able to hold as many
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pipeline output value cycles as there are non-stallable stages in the pipeline.
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As an example, the following 6 stage pipeline will have the following valid
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signals: <img title="Stage control" src="includes/img/Pipeline/ns_ex1.png"/>
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### Example 1:
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In this example, we have two NS stages followed by three runoff stages:
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<img title="Stage control" src="includes/img/Pipeline/ns_ex2.png"/>
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In this example we see that, as expected, two cycles are output from the
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pipeline after the stall signal goes high, corresponding to the two NS stages.
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### Example 2:
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In this example, we have two NS stages, then one runoff stage, then one NS
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stage, and finally one runoff stage:
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<img title="Stage control" src="includes/img/Pipeline/ns_ex3.png"/>
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In this example we see that, as expected, three cycles are output from the
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pipeline after the stall signal goes high, corresponding to the three NS stages.
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@ -24,6 +24,24 @@ namespace pipeline {
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class StageOp;
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class ScheduledPipelineOp;
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// StageKind defines the control semantics of a pipeline stages.
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enum class StageKind {
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// All stages in a pipeline without a stall signal is a continuous stage.
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Continuous,
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// Stallable stages are any stages which appear **before** the first
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// non-stallable stage in the pipeline.
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Stallable,
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// Non-stallable stages are the stages explicitly marked as non-stallable by
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// the user.
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NonStallable,
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// Runoff stages and stages that appear **after** (and by extension,
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// **between** non-stallable stages). Runoff stages consider their own
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// enablement wrt. the stall signal, as well as the enablement of the **last
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// non-stallable register** (LNS) wrt. the runoff stage's position in the
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// pipeline.
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Runoff
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};
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namespace detail {
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// Returns the set of values defined outside of the given region, and the
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@ -27,12 +27,6 @@ class PipelineBase<string mnemonic, list<Trait> traits = []> :
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Pure,
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RegionKindInterface,
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AttrSizedOperandSegments])> {
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let arguments = (ins
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OptionalAttr<StrAttr>:$name, Variadic<AnyType>:$inputs, Optional<I1>:$stall,
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I1:$clock, I1:$reset, I1:$go, StrArrayAttr:$inputNames,
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StrArrayAttr:$outputNames
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);
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let results = (outs Variadic<AnyType>:$dataOutputs, I1:$done);
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let hasCustomAssemblyFormat = 1;
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@ -117,6 +111,11 @@ def UnscheduledPipelineOp : PipelineBase<"unscheduled", [
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about the interface signals.
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}];
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let arguments = (ins
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OptionalAttr<StrAttr>:$name, Variadic<AnyType>:$inputs, Optional<I1>:$stall,
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I1:$clock, I1:$reset, I1:$go, StrArrayAttr:$inputNames,
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StrArrayAttr:$outputNames
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);
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let regions = (region SizedRegion<1>: $body);
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let extraModuleClassDeclaration = "";
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}
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@ -148,19 +147,48 @@ def ScheduledPipelineOp : PipelineBase<"scheduled", [
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Any value defined outside the pipeline is considered an external input. An
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external input will _not_ be registered.
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The pipeline may optionally be provided with an array of bits `stallability`
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which is used to determine which stages are stallable.
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- If not provided and the pipeline has a stall signal, all stages are stallable.
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- If provided, and the pipeline has a stall signal, the number of bits must
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match the number of stages in the pipeline. Each bit represents a stage,
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in the order of which the stages appear wrt. the `pipeline.stage` operations.
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A bit set to 1 indicates that the stage is stallable, and 0 indicates that
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the stage is not stallable.
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The exit (non-registered) stage of a pipeline cannot be non-stallable, and
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will always follow the stallability of the parent pipeline.
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For more information about non-stallable stages, and how these are lowered,
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please refer to the Pipeline dialect rationale.
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}];
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let arguments = (ins
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OptionalAttr<StrAttr>:$name,
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Variadic<AnyType>:$inputs,
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Optional<I1>:$stall,
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I1:$clock, I1:$reset, I1:$go,
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StrArrayAttr:$inputNames, StrArrayAttr:$outputNames,
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OptionalAttr<BoolArrayAttr>:$stallability
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);
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let regions = (region AnyRegion:$body);
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let hasVerifier = 1;
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let skipDefaultBuilders = 1;
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let builders = [
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OpBuilder<(ins "TypeRange":$dataOutputs, "ValueRange":$inputs,
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OpBuilder<(ins
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"TypeRange":$dataOutputs,
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"ValueRange":$inputs,
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"ArrayAttr":$inputNames, "ArrayAttr":$outputNames,
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"Value":$clock, "Value":$reset, "Value":$go, CArg<"Value", "{}">:$stall, CArg<"StringAttr", "{}">:$name)>
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"Value":$clock, "Value":$reset, "Value":$go,
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CArg<"Value", "{}">:$stall,
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CArg<"StringAttr", "{}">:$name,
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CArg<"ArrayAttr", "{}">:$stallability
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)>
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];
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code extraModuleClassDeclaration = [{
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static mlir::RegionKind getRegionKind(unsigned index) {
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return mlir::RegionKind::SSACFG;
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@ -171,6 +199,10 @@ def ScheduledPipelineOp : PipelineBase<"scheduled", [
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return getRegion().getBlocks();
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}
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size_t getNumStages() {
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return getStages().size();
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}
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void getAsmBlockArgumentNames(mlir::Region ®ion,
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mlir::OpAsmSetValueNameFn setNameFn);
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@ -227,6 +259,9 @@ def ScheduledPipelineOp : PipelineBase<"scheduled", [
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return stage->getArguments().back();
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return getInnerGo();
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}
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// Returns the stage kind of the given stage index.
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StageKind getStageKind(size_t stageIdx);
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}];
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}
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@ -1,6 +1,6 @@
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import glob, os
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dir_path = os.path.dirname(os.path.realpath(__file__))
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for pyfile in glob.glob(os.path.join(dir_path, "**", "*.py")):
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for pyfile in glob.glob(os.path.join(dir_path, "**", "*.py"), recursive=True):
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# remove dir from pyfile
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config.excludes.add(os.path.basename(pyfile))
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@ -0,0 +1,87 @@
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import cocotb
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from cocotb.triggers import Timer
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import cocotb.clock
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# Value that will be adjusted and assigned to the dut input argument, every
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# clock cycle. This is mainly to assist manual verification of the VCD trace/
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v = 1
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async def clock(dut):
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global v
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dut.clock.value = 0
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await Timer(1, units='ns')
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v += 1
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dut.arg0.value = v
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dut.clock.value = 1
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await Timer(1, units='ns')
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async def initDut(dut):
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"""
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Initializes a dut by adding a clock, setting initial valid and ready flags,
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and performing a reset.
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"""
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# Reset
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dut.reset.value = 1
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await clock(dut)
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dut.reset.value = 0
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await clock(dut)
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async def nonstallable_test(dut, stageStallability):
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"""
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Runs a test of a non-stallable pipeline.
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Provided the number of stages in the pipeline and the indices of the non-stallable
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stages, the test will:
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1. for NStallCycles : range(0 to nStages - 1):
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1. for fillCycles : range(0 to nStages - 1):
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1. fill the pipeline with $fillCycles valid tokens
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2. raise the stall signal
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3. wait for NStallCycles
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4. While doing so, check that len(nonStallableStageIdxs) dut.done assertions
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occur
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5. deassert stall
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6. check that the expected amount of bubbles exit the pipeline
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"""
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nStages = len(stageStallability)
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numNonstallableStages = sum(
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[1 if not stallable else 0 for stallable in stageStallability])
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for nStallCycles in range(0, nStages * 2):
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for fillCycles in range(0, nStages + 1):
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print(f"nStallCycles: {nStallCycles}, fillCycles: {fillCycles}")
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# Reset the dut
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dut.go.value = 0
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dut.stall.value = 0
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dut.arg0.value = 42
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await initDut(dut)
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dut.stall.value = 0
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# Fill the pipeline with fillCycles valid tokens
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dut.go.value = 1
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for i in range(fillCycles):
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await clock(dut)
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dut.go.value = 0
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nBufferedTokensExpected = min(numNonstallableStages, nStallCycles,
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fillCycles)
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nBubblesExpected = nBufferedTokensExpected
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# Raise the stall signal. We now expect that numNonStallableStages dut.done
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# assertions will occur in a row.
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sequence = []
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dut.stall.value = 1
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for cycle in range(nStallCycles + nStages):
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if cycle > nStallCycles:
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dut.stall.value = 0
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await Timer(1, units='ns')
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sequence.append(int(dut.done))
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await clock(dut)
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# Check that exactly fill_cycles tokens exited the pipeline
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nTokensExited = sum(sequence)
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assert nTokensExited == fillCycles, f"Expected {fillCycles} tokens to exit the pipeline, but {nTokensExited} did"
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@ -0,0 +1,30 @@
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// REQUIRES: iverilog,cocotb
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// RUN: circt-opt %s -pipeline-explicit-regs -lower-pipeline-to-hw -lower-seq-to-sv -sv-trace-iverilog -export-verilog \
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// RUN: -o %t.mlir > %t.sv
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// RUN: circt-cocotb-driver.py --objdir=%T --topLevel=nonstallable_test1 \
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// RUN: --pythonModule=nonstallable_test1 --pythonFolder="%S,%S/.." %t.sv 2>&1 | FileCheck %s
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// CHECK: ** TEST
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// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
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hw.module @nonstallable_test1(%arg0: i32, %go: i1, %clock: i1, %reset: i1, %stall: i1) -> (out: i32, done: i1) {
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%out, %done = pipeline.scheduled "nonstallable_test1"(%a0 : i32 = %arg0)
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stall(%s = %stall) clock(%c = %clock) reset(%r = %reset) go(%g = %go)
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{stallability = [true, false, false, true, true]} -> (out : i32) {
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pipeline.stage ^bb1
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^bb1(%s1_enable: i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable: i1):
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pipeline.stage ^bb3
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^bb3(%s3_enable: i1):
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pipeline.stage ^bb4
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^bb4(%s4_enable: i1):
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pipeline.stage ^bb5
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^bb5(%s5_enable: i1):
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pipeline.return %a0 : i32
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}
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hw.output %out, %done : i32, i1
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}
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@ -0,0 +1,7 @@
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import cocotb
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from nonstallable_helper import nonstallable_test
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@cocotb.test()
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async def test1(dut):
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await nonstallable_test(dut, [0, 1, 1, 0, 0])
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@ -0,0 +1,30 @@
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// REQUIRES: iverilog,cocotb
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// RUN: circt-opt %s -pipeline-explicit-regs -lower-pipeline-to-hw -lower-seq-to-sv -sv-trace-iverilog -export-verilog \
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// RUN: -o %t.mlir > %t.sv
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// RUN: circt-cocotb-driver.py --objdir=%T --topLevel=nonstallable_test2 \
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// RUN: --pythonModule=nonstallable_test2 --pythonFolder="%S,%S/.." %t.sv 2>&1 | FileCheck %s
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// CHECK: ** TEST
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// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
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hw.module @nonstallable_test2(%arg0: i32, %go: i1, %clock: i1, %reset: i1, %stall: i1) -> (out: i32, done : i1) {
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%out, %done = pipeline.scheduled "nonstallable_test2"(%a0 : i32 = %arg0)
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stall(%s = %stall) clock(%c = %clock) reset(%r = %reset) go(%g = %go)
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{stallability = [true, false, true, false, true]} -> (out : i32) {
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pipeline.stage ^bb1
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^bb1(%s1_enable: i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable: i1):
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pipeline.stage ^bb3
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^bb3(%s3_enable: i1):
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pipeline.stage ^bb4
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^bb4(%s4_enable: i1):
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pipeline.stage ^bb5
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^bb5(%s5_enable: i1):
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pipeline.return %a0 : i32
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}
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hw.output %out, %done : i32, i1
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}
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@ -0,0 +1,8 @@
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import cocotb
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from nonstallable_helper import nonstallable_test
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@cocotb.test()
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async def test1(dut):
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await nonstallable_test(dut, [0, 1, 0, 1, 0])
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@ -46,6 +46,7 @@ public:
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Value stall;
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Value clock;
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Value reset;
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Value lnsEn;
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};
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// Arguments used for returning the results from a stage. These values must
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@ -54,6 +55,11 @@ public:
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llvm::SmallVector<Value> regs;
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llvm::SmallVector<Value> passthroughs;
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Value valid;
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// In case this was the last register in a non-stallable register chain, the
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// register will also return its enable signal to be used for LNS of
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// downstream stages.
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Value lnsEn;
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};
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virtual FailureOr<StageReturns>
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@ -89,6 +95,41 @@ public:
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}
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}
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auto loc = terminator->getLoc();
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Value notStalled;
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auto getOrSetNotStalled = [&]() {
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if (!notStalled) {
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notStalled = comb::createOrFoldNot(loc, args.stall, builder);
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}
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return notStalled;
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};
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// Determine the stage kind. This will influence how the stage valid and
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// enable signals are defined.
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StageKind stageKind = pipeline.getStageKind(stageIndex);
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Value stageValid;
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StringAttr validSignalName =
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builder.getStringAttr(getStagePrefix(stageIndex).strref() + "_valid");
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switch (stageKind) {
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case StageKind::Continuous:
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LLVM_FALLTHROUGH;
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case StageKind::NonStallable:
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stageValid = args.enable;
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break;
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case StageKind::Stallable:
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stageValid =
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builder.create<comb::AndOp>(loc, args.enable, getOrSetNotStalled());
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stageValid.getDefiningOp()->setAttr("sv.namehint", validSignalName);
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break;
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case StageKind::Runoff:
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assert(args.lnsEn && "Expected an LNS signal if this was a runoff stage");
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stageValid = builder.create<comb::AndOp>(
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loc, args.enable,
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builder.create<comb::OrOp>(loc, args.lnsEn, getOrSetNotStalled()));
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stageValid.getDefiningOp()->setAttr("sv.namehint", validSignalName);
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break;
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}
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StageReturns rets;
|
||||
auto stageOp = dyn_cast<StageOp>(terminator);
|
||||
if (!stageOp) {
|
||||
|
|
@ -97,32 +138,19 @@ public:
|
|||
// register its operands, hence, all return operands are passthrough
|
||||
// and the valid signal is equal to the unregistered enable signal.
|
||||
rets.passthroughs = terminator->getOperands();
|
||||
rets.valid = args.enable;
|
||||
rets.valid = stageValid;
|
||||
return rets;
|
||||
}
|
||||
|
||||
assert(registerNames.size() == stageOp.getRegisters().size() &&
|
||||
"register names and registers must be the same size");
|
||||
|
||||
// Build data registers.
|
||||
auto stageRegPrefix = getStageRegPrefix(stageIndex);
|
||||
auto loc = stageOp->getLoc();
|
||||
|
||||
// Build the clock enable signal: enable && !stall (if applicable)
|
||||
Value stageValidAndNotStalled = args.enable;
|
||||
Value notStalled;
|
||||
bool hasStall = static_cast<bool>(args.stall);
|
||||
if (hasStall) {
|
||||
notStalled = comb::createOrFoldNot(loc, args.stall, builder);
|
||||
stageValidAndNotStalled =
|
||||
builder.create<comb::AndOp>(loc, stageValidAndNotStalled, notStalled);
|
||||
}
|
||||
|
||||
bool isStallablePipeline = stageKind != StageKind::Continuous;
|
||||
Value notStalledClockGate;
|
||||
if (this->clockGateRegs) {
|
||||
// Create the top-level clock gate.
|
||||
notStalledClockGate = builder.create<seq::ClockGateOp>(
|
||||
loc, args.clock, stageValidAndNotStalled, /*test_enable=*/Value(),
|
||||
loc, args.clock, stageValid, /*test_enable=*/Value(),
|
||||
/*inner_sym=*/hw::InnerSymAttr());
|
||||
}
|
||||
|
||||
|
|
@ -138,18 +166,19 @@ public:
|
|||
for (auto hierClockGateEnable : stageOp.getClockGatesForReg(regIdx)) {
|
||||
// Create clock gates for any hierarchically nested clock gates.
|
||||
currClockGate = builder.create<seq::ClockGateOp>(
|
||||
loc, currClockGate, hierClockGateEnable, /*test_enable=*/Value(),
|
||||
loc, currClockGate, hierClockGateEnable,
|
||||
/*test_enable=*/Value(),
|
||||
/*inner_sym=*/hw::InnerSymAttr());
|
||||
}
|
||||
dataReg = builder.create<seq::CompRegOp>(stageOp->getLoc(), regIn,
|
||||
currClockGate, regName);
|
||||
} else {
|
||||
// Only clock-enable the register if the pipeline is stallable.
|
||||
// For non-stallable pipelines, a data register can always be clocked.
|
||||
if (hasStall) {
|
||||
// For non-stallable (continuous) pipelines, a data register can always
|
||||
// be clocked.
|
||||
if (isStallablePipeline) {
|
||||
dataReg = builder.create<seq::CompRegClockEnabledOp>(
|
||||
stageOp->getLoc(), regIn, args.clock, stageValidAndNotStalled,
|
||||
regName);
|
||||
stageOp->getLoc(), regIn, args.clock, stageValid, regName);
|
||||
} else {
|
||||
dataReg = builder.create<seq::CompRegOp>(stageOp->getLoc(), regIn,
|
||||
args.clock, regName);
|
||||
|
|
@ -158,38 +187,26 @@ public:
|
|||
rets.regs.push_back(dataReg);
|
||||
}
|
||||
|
||||
// Build valid register. The valid register is always reset to 0, and
|
||||
// clock enabled when not stalling.
|
||||
auto validRegName = (stageRegPrefix.strref() + "_valid").str();
|
||||
Value validRegResetVal =
|
||||
builder.create<hw::ConstantOp>(terminator->getLoc(), APInt(1, 0, false))
|
||||
.getResult();
|
||||
if (hasStall) {
|
||||
rets.valid = builder.create<seq::CompRegClockEnabledOp>(
|
||||
loc, args.enable, args.clock, notStalled, args.reset,
|
||||
validRegResetVal, validRegName);
|
||||
} else {
|
||||
rets.valid = builder.create<seq::CompRegOp>(loc, args.enable, args.clock,
|
||||
args.reset, validRegResetVal,
|
||||
validRegName);
|
||||
}
|
||||
rets.valid = stageValid;
|
||||
if (stageKind == StageKind::NonStallable)
|
||||
rets.lnsEn = args.enable;
|
||||
|
||||
rets.passthroughs = stageOp.getPassthroughs();
|
||||
return rets;
|
||||
}
|
||||
|
||||
// A container carrying all-things stage output naming related.
|
||||
// To avoid overloading 'output's to much (i'm trying to keep that reserved
|
||||
// for "output" ports), this is named "egress".
|
||||
// To avoid overloading 'output's to much (i'm trying to keep that
|
||||
// reserved for "output" ports), this is named "egress".
|
||||
struct StageEgressNames {
|
||||
llvm::SmallVector<Attribute> regNames;
|
||||
llvm::SmallVector<Attribute> outNames;
|
||||
llvm::SmallVector<Attribute> inNames;
|
||||
};
|
||||
|
||||
// Returns a set of names for the output values of a given stage (registers
|
||||
// and passthrough). If `withPipelinePrefix` is true, the names will be
|
||||
// prefixed with the pipeline name.
|
||||
// Returns a set of names for the output values of a given stage
|
||||
// (registers and passthrough). If `withPipelinePrefix` is true, the names
|
||||
// will be prefixed with the pipeline name.
|
||||
void getStageEgressNames(size_t stageIndex, Operation *stageTerminator,
|
||||
bool withPipelinePrefix,
|
||||
StageEgressNames &egressNames) {
|
||||
|
|
@ -243,15 +260,15 @@ public:
|
|||
egressNames.inNames.push_back(builder.getStringAttr(assignedInName));
|
||||
}
|
||||
} else {
|
||||
// For the return op, we just inherit the names of the top-level pipeline
|
||||
// as stage output names.
|
||||
// For the return op, we just inherit the names of the top-level
|
||||
// pipeline as stage output names.
|
||||
llvm::copy(pipeline.getOutputNames().getAsRange<StringAttr>(),
|
||||
std::back_inserter(egressNames.outNames));
|
||||
}
|
||||
}
|
||||
|
||||
// Returns a string to be used as a prefix for all stage registers.
|
||||
virtual StringAttr getStageRegPrefix(size_t stageIdx) = 0;
|
||||
virtual StringAttr getStagePrefix(size_t stageIdx) = 0;
|
||||
|
||||
protected:
|
||||
// Determine a reasonable name for the pipeline. This will affect naming
|
||||
|
|
@ -288,7 +305,7 @@ class PipelineInlineLowering : public PipelineLowering {
|
|||
public:
|
||||
using PipelineLowering::PipelineLowering;
|
||||
|
||||
StringAttr getStageRegPrefix(size_t stageIdx) override {
|
||||
StringAttr getStagePrefix(size_t stageIdx) override {
|
||||
return builder.getStringAttr(pipelineName.strref() + "_stage" +
|
||||
Twine(stageIdx));
|
||||
}
|
||||
|
|
@ -328,6 +345,8 @@ public:
|
|||
lowerStage(Block *stage, StageArgs args, size_t stageIndex,
|
||||
llvm::ArrayRef<Attribute> /*inputNames*/ = {}) override {
|
||||
OpBuilder::InsertionGuard guard(builder);
|
||||
Operation *terminator = stage->getTerminator();
|
||||
Location loc = terminator->getLoc();
|
||||
|
||||
if (stage != pipeline.getEntryStage()) {
|
||||
// Replace the internal stage inputs with the provided arguments.
|
||||
|
|
@ -336,11 +355,55 @@ public:
|
|||
vInput.replaceAllUsesWith(vArg);
|
||||
}
|
||||
|
||||
// Build stage enable register. The enable register is always reset to 0.
|
||||
// The stage enable register takes the previous-stage combinational valid
|
||||
// output and determines whether this stage is active or not in the next
|
||||
// cycle.
|
||||
// A non-stallable stage always registers the incoming enable signal,
|
||||
// whereas other stages register based on the current stall state.
|
||||
StageKind stageKind = pipeline.getStageKind(stageIndex);
|
||||
Value stageEnabled;
|
||||
if (stageIndex == 0) {
|
||||
stageEnabled = args.enable;
|
||||
} else {
|
||||
auto stageRegPrefix = getStagePrefix(stageIndex);
|
||||
auto enableRegName = (stageRegPrefix.strref() + "_enable").str();
|
||||
Value enableRegResetVal =
|
||||
builder.create<hw::ConstantOp>(loc, APInt(1, 0, false)).getResult();
|
||||
|
||||
switch (stageKind) {
|
||||
case StageKind::Continuous:
|
||||
LLVM_FALLTHROUGH;
|
||||
case StageKind::NonStallable:
|
||||
stageEnabled = builder.create<seq::CompRegOp>(
|
||||
loc, args.enable, args.clock, args.reset, enableRegResetVal,
|
||||
enableRegName);
|
||||
break;
|
||||
case StageKind::Stallable:
|
||||
stageEnabled = builder.create<seq::CompRegClockEnabledOp>(
|
||||
loc, args.enable, args.clock,
|
||||
comb::createOrFoldNot(loc, args.stall, builder), args.reset,
|
||||
enableRegResetVal, enableRegName);
|
||||
break;
|
||||
case StageKind::Runoff:
|
||||
assert(args.lnsEn &&
|
||||
"Expected an LNS signal if this was a runoff stage");
|
||||
stageEnabled = builder.create<seq::CompRegClockEnabledOp>(
|
||||
loc, args.enable, args.clock,
|
||||
builder.create<comb::OrOp>(
|
||||
loc, args.lnsEn,
|
||||
comb::createOrFoldNot(loc, args.stall, builder)),
|
||||
args.reset, enableRegResetVal, enableRegName);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Replace the stage valid signal.
|
||||
pipeline.getStageEnableSignal(stage).replaceAllUsesWith(args.enable);
|
||||
args.enable = stageEnabled;
|
||||
pipeline.getStageEnableSignal(stage).replaceAllUsesWith(stageEnabled);
|
||||
|
||||
// Determine stage egress info.
|
||||
auto nextStage = dyn_cast<StageOp>(stage->getTerminator());
|
||||
auto nextStage = dyn_cast<StageOp>(terminator);
|
||||
StageEgressNames egressNames;
|
||||
if (nextStage)
|
||||
getStageEgressNames(stageIndex, nextStage,
|
||||
|
|
@ -357,6 +420,11 @@ public:
|
|||
llvm::append_range(nextStageArgs, stageRets.regs);
|
||||
llvm::append_range(nextStageArgs, stageRets.passthroughs);
|
||||
args.enable = stageRets.valid;
|
||||
if (stageRets.lnsEn) {
|
||||
// Swap the lnsEn signal if the current stage lowering generated an
|
||||
// lnsEn.
|
||||
args.lnsEn = stageRets.lnsEn;
|
||||
}
|
||||
args.data = nextStageArgs;
|
||||
return lowerStage(nextStage.getNextStage(), args, stageIndex + 1);
|
||||
}
|
||||
|
|
@ -366,7 +434,7 @@ public:
|
|||
llvm::SmallVector<Value> pipelineReturns;
|
||||
llvm::append_range(pipelineReturns, returnOp.getInputs());
|
||||
// The last stage valid signal is the 'done' output of the pipeline.
|
||||
pipelineReturns.push_back(args.enable);
|
||||
pipelineReturns.push_back(stageRets.valid);
|
||||
pipeline.replaceAllUsesWith(pipelineReturns);
|
||||
return stageRets;
|
||||
}
|
||||
|
|
@ -382,8 +450,8 @@ struct PipelineToHWPass : public PipelineToHWBase<PipelineToHWPass> {
|
|||
|
||||
private:
|
||||
// Lowers pipelines within HWModules. This pass is currently expecting that
|
||||
// Pipelines are always nested with HWModule's but could be written to be more
|
||||
// generic.
|
||||
// Pipelines are always nested with HWModule's but could be written to be
|
||||
// more generic.
|
||||
void runOnHWModule(hw::HWModuleOp mod);
|
||||
};
|
||||
|
||||
|
|
@ -396,8 +464,8 @@ void PipelineToHWPass::runOnHWModule(hw::HWModuleOp mod) {
|
|||
OpBuilder builder(&getContext());
|
||||
// Iterate over each pipeline op in the module and convert.
|
||||
// Note: This pass matches on `hw::ModuleOp`s and not directly on the
|
||||
// `ScheduledPipelineOp` due to the `ScheduledPipelineOp` being erased during
|
||||
// this pass.
|
||||
// `ScheduledPipelineOp` due to the `ScheduledPipelineOp` being erased
|
||||
// during this pass.
|
||||
size_t pipelinesSeen = 0;
|
||||
for (auto pipeline :
|
||||
llvm::make_early_inc_range(mod.getOps<ScheduledPipelineOp>())) {
|
||||
|
|
|
|||
|
|
@ -269,15 +269,15 @@ static void printPipelineOp(OpAsmPrinter &p, TPipelineOp op) {
|
|||
printKeywordAssignment(p, "reset", op.getInnerReset(), op.getReset());
|
||||
p << " ";
|
||||
printKeywordAssignment(p, "go", op.getInnerGo(), op.getGo());
|
||||
// Print the optional attribute dict.
|
||||
p.printOptionalAttrDict(op->getAttrs(),
|
||||
/*elidedAttrs=*/{"name", "operandSegmentSizes",
|
||||
"outputNames", "inputNames"});
|
||||
p << " -> ";
|
||||
|
||||
// Print the output list.
|
||||
printOutputList(p, op.getDataOutputs().getTypes(), op.getOutputNames());
|
||||
|
||||
// Print the optional attribute dict.
|
||||
p.printOptionalAttrDict(op->getAttrs(),
|
||||
/*elidedAttrs=*/{"name", "operandSegmentSizes",
|
||||
"outputNames", "inputNames"});
|
||||
p << " ";
|
||||
|
||||
// Print the inner region, eliding the entry block arguments - we've already
|
||||
|
|
@ -314,7 +314,7 @@ void ScheduledPipelineOp::build(OpBuilder &odsBuilder, OperationState &odsState,
|
|||
TypeRange dataOutputs, ValueRange inputs,
|
||||
ArrayAttr inputNames, ArrayAttr outputNames,
|
||||
Value clock, Value reset, Value go, Value stall,
|
||||
StringAttr name) {
|
||||
StringAttr name, ArrayAttr stallability) {
|
||||
odsState.addOperands(inputs);
|
||||
if (stall)
|
||||
odsState.addOperands(stall);
|
||||
|
|
@ -359,6 +359,9 @@ void ScheduledPipelineOp::build(OpBuilder &odsBuilder, OperationState &odsState,
|
|||
|
||||
// entry stage valid signal.
|
||||
entryBlock.addArgument(i1, odsState.location);
|
||||
|
||||
if (stallability)
|
||||
odsState.addAttribute("stallability", stallability);
|
||||
}
|
||||
|
||||
Block *ScheduledPipelineOp::addStage() {
|
||||
|
|
@ -558,9 +561,61 @@ LogicalResult ScheduledPipelineOp::verify() {
|
|||
}
|
||||
}
|
||||
|
||||
if (auto stallability = getStallability()) {
|
||||
// Only allow specifying stallability if there is a stall signal.
|
||||
if (!hasStall())
|
||||
return emitOpError("cannot specify stallability without a stall signal.");
|
||||
|
||||
// Ensure that the # of stages is equal to the length of the stallability
|
||||
// array - the exit stage is never stallable.
|
||||
size_t nRegisterStages = stages.size() - 1;
|
||||
if (stallability->size() != nRegisterStages)
|
||||
return emitOpError("stallability array must be the same length as the "
|
||||
"number of stages. Pipeline has ")
|
||||
<< nRegisterStages << " stages but array had "
|
||||
<< stallability->size() << " elements.";
|
||||
}
|
||||
|
||||
return success();
|
||||
}
|
||||
|
||||
StageKind ScheduledPipelineOp::getStageKind(size_t stageIndex) {
|
||||
size_t nStages = getNumStages();
|
||||
assert(stageIndex < nStages && "invalid stage index");
|
||||
|
||||
if (!hasStall())
|
||||
return StageKind::Continuous;
|
||||
|
||||
// There is a stall signal - also check whether stage-level stallability is
|
||||
// specified.
|
||||
std::optional<ArrayAttr> stallability = getStallability();
|
||||
if (!stallability) {
|
||||
// All stages are stallable.
|
||||
return StageKind::Stallable;
|
||||
}
|
||||
|
||||
if (stageIndex < stallability->size()) {
|
||||
bool stageIsStallable =
|
||||
(*stallability)[stageIndex].cast<BoolAttr>().getValue();
|
||||
if (!stageIsStallable) {
|
||||
// This is a non-stallable stage.
|
||||
return StageKind::NonStallable;
|
||||
}
|
||||
}
|
||||
|
||||
// Walk backwards from this stage to see if any non-stallable stage exists.
|
||||
// If so, this is a runoff stage.
|
||||
// TODO: This should be a pre-computed property.
|
||||
if (stageIndex == 0)
|
||||
return StageKind::Stallable;
|
||||
|
||||
for (size_t i = stageIndex - 1; i > 0; --i) {
|
||||
if (getStageKind(i) == StageKind::NonStallable)
|
||||
return StageKind::Runoff;
|
||||
}
|
||||
return StageKind::Stallable;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ReturnOp
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -15,15 +15,15 @@ hw.module @testBasic(%arg0: i1, %clk: i1, %rst: i1) -> (out: i1) {
|
|||
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32, %[[VAL_2:.*]]: i1, %[[VAL_3:.*]]: i1, %[[VAL_4:.*]]: i1) -> (out: i32, done: i1) {
|
||||
// CHECK: %[[VAL_5:.*]] = comb.add %[[VAL_0]], %[[VAL_0]] : i32
|
||||
// CHECK: %[[VAL_6:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_6]] : i1
|
||||
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_6]] : i1
|
||||
// CHECK: %[[VAL_8:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage1_valid %[[VAL_7]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage2_enable %[[VAL_7]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_10:.*]] = seq.compreg sym @p0_stage2_reg0 %[[VAL_5]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_11:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_12:.*]] = seq.compreg sym @p0_stage2_valid %[[VAL_9]], %[[VAL_3]], %[[VAL_4]], %[[VAL_11]] : i1
|
||||
// CHECK: %[[VAL_12:.*]] = seq.compreg sym @p0_stage3_enable %[[VAL_9]], %[[VAL_3]], %[[VAL_4]], %[[VAL_11]] : i1
|
||||
// CHECK: %[[VAL_13:.*]] = seq.compreg sym @p0_stage3_reg0 %[[VAL_10]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_14:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_15:.*]] = seq.compreg sym @p0_stage3_valid %[[VAL_12]], %[[VAL_3]], %[[VAL_4]], %[[VAL_14]] : i1
|
||||
// CHECK: %[[VAL_15:.*]] = seq.compreg sym @p0_stage4_enable %[[VAL_12]], %[[VAL_3]], %[[VAL_4]], %[[VAL_14]] : i1
|
||||
// CHECK: hw.output %[[VAL_13]], %[[VAL_15]] : i32, i1
|
||||
// CHECK: }
|
||||
hw.module @testLatency1(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) -> (out: i32, done: i1) {
|
||||
|
|
@ -51,7 +51,7 @@ hw.module @testLatency1(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) ->
|
|||
// CHECK: %[[VAL_6:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_8:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_10:.*]] = comb.add %[[VAL_6]], %[[VAL_7]] : i32
|
||||
// CHECK: hw.output %[[VAL_10]], %[[VAL_9]] : i32, i1
|
||||
// CHECK: }
|
||||
|
|
@ -72,23 +72,23 @@ hw.module @testSingle(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) -> (o
|
|||
// CHECK: %[[VAL_6:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_8:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_10:.*]] = comb.add %[[VAL_6]], %[[VAL_7]] : i32
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg sym @p0_stage1_reg0 %[[VAL_10]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_12:.*]] = seq.compreg sym @p0_stage1_reg1 %[[VAL_6]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_13:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_14:.*]] = seq.compreg sym @p0_stage1_valid %[[VAL_9]], %[[VAL_3]], %[[VAL_4]], %[[VAL_13]] : i1
|
||||
// CHECK: %[[VAL_14:.*]] = seq.compreg sym @p0_stage2_enable %[[VAL_9]], %[[VAL_3]], %[[VAL_4]], %[[VAL_13]] : i1
|
||||
// CHECK: %[[VAL_15:.*]] = comb.mul %[[VAL_11]], %[[VAL_12]] : i32
|
||||
// CHECK: %[[VAL_16:.*]] = comb.sub %[[VAL_15]], %[[VAL_1]] : i32
|
||||
// CHECK: %[[VAL_17:.*]] = seq.compreg sym @p1_stage0_reg0 %[[VAL_16]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_18:.*]] = seq.compreg sym @p1_stage0_reg1 %[[VAL_15]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_19:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_20:.*]] = seq.compreg sym @p1_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_19]] : i1
|
||||
// CHECK: %[[VAL_20:.*]] = seq.compreg sym @p1_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_19]] : i1
|
||||
// CHECK: %[[VAL_21:.*]] = comb.add %[[VAL_17]], %[[VAL_18]] : i32
|
||||
// CHECK: %[[VAL_22:.*]] = seq.compreg sym @p1_stage1_reg0 %[[VAL_21]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_23:.*]] = seq.compreg sym @p1_stage1_reg1 %[[VAL_17]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_24:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_25:.*]] = seq.compreg sym @p1_stage1_valid %[[VAL_20]], %[[VAL_3]], %[[VAL_4]], %[[VAL_24]] : i1
|
||||
// CHECK: %[[VAL_25:.*]] = seq.compreg sym @p1_stage2_enable %[[VAL_20]], %[[VAL_3]], %[[VAL_4]], %[[VAL_24]] : i1
|
||||
// CHECK: %[[VAL_26:.*]] = comb.mul %[[VAL_22]], %[[VAL_23]] : i32
|
||||
// CHECK: hw.output %[[VAL_15]], %[[VAL_14]] : i32, i1
|
||||
// CHECK: }
|
||||
|
|
@ -124,11 +124,11 @@ hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) ->
|
|||
// CHECK: %[[VAL_6:.*]] = comb.sub %[[VAL_0]], %[[VAL_0]] : i32
|
||||
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_6]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_8:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_8]] : i1
|
||||
// CHECK: %[[VAL_10:.*]] = comb.add %[[VAL_7]], %[[VAL_1]] : i32
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg sym @p0_stage1_reg0 %[[VAL_10]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_12:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_13:.*]] = seq.compreg sym @p0_stage1_valid %[[VAL_9]], %[[VAL_3]], %[[VAL_4]], %[[VAL_12]] : i1
|
||||
// CHECK: %[[VAL_13:.*]] = seq.compreg sym @p0_stage2_enable %[[VAL_9]], %[[VAL_3]], %[[VAL_4]], %[[VAL_12]] : i1
|
||||
// CHECK: hw.output %[[VAL_11]], %[[VAL_1]] : i32, i32
|
||||
// CHECK: }
|
||||
hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %go : i1, %clk: i1, %rst: i1) -> (out0: i32, out1: i32) {
|
||||
|
|
@ -159,7 +159,7 @@ hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %go : i1, %clk: i1, %rst: i
|
|||
// CHECK: sv.assign %[[VAL_5]], %[[VAL_8]] : i32
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_8]], %[[VAL_2]] : i32
|
||||
// CHECK: %[[VAL_10:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_1]], %[[VAL_2]], %[[VAL_3]], %[[VAL_10]] : i1
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_1]], %[[VAL_2]], %[[VAL_3]], %[[VAL_10]] : i1
|
||||
// CHECK: %[[VAL_12:.*]] = sv.wire : !hw.inout<i32>
|
||||
// CHECK: %[[VAL_13:.*]] = sv.read_inout %[[VAL_12]] : !hw.inout<i32>
|
||||
// CHECK: %[[VAL_14:.*]] = comb.add %[[VAL_13]], %[[VAL_9]] : i32
|
||||
|
|
@ -167,7 +167,7 @@ hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %go : i1, %clk: i1, %rst: i
|
|||
// CHECK: sv.assign %[[VAL_12]], %[[VAL_15]] : i32
|
||||
// CHECK: %[[VAL_16:.*]] = seq.compreg sym @p0_stage1_reg0 %[[VAL_15]], %[[VAL_2]] : i32
|
||||
// CHECK: %[[VAL_17:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_18:.*]] = seq.compreg sym @p0_stage1_valid %[[VAL_11]], %[[VAL_2]], %[[VAL_3]], %[[VAL_17]] : i1
|
||||
// CHECK: %[[VAL_18:.*]] = seq.compreg sym @p0_stage2_enable %[[VAL_11]], %[[VAL_2]], %[[VAL_3]], %[[VAL_17]] : i1
|
||||
// CHECK: %[[VAL_19:.*]] = sv.wire : !hw.inout<i32>
|
||||
// CHECK: %[[VAL_20:.*]] = sv.read_inout %[[VAL_19]] : !hw.inout<i32>
|
||||
// CHECK: %[[VAL_21:.*]] = comb.add %[[VAL_20]], %[[VAL_16]] : i32
|
||||
|
|
@ -211,11 +211,16 @@ hw.module @testControlUsage(%arg0: i32, %go : i1, %clk: i1, %rst: i1) -> (out0:
|
|||
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i1, %[[VAL_2:.*]]: i1, %[[VAL_3:.*]]: i1, %[[VAL_4:.*]]: i1) -> (out0: i32, out1: i1) {
|
||||
// CHECK: %[[VAL_5:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_6:.*]] = comb.xor %[[VAL_2]], %[[VAL_5]] : i1
|
||||
// CHECK: %[[VAL_7:.*]] = comb.and %[[VAL_1]], %[[VAL_6]] : i1
|
||||
// CHECK: %[[VAL_8:.*]] = seq.compreg.ce sym @p0_stage0_reg0 %[[VAL_0]], %[[VAL_3]], %[[VAL_7]] : i32
|
||||
// CHECK: %[[VAL_7:.*]] = comb.and %[[VAL_1]], %[[VAL_6]]
|
||||
// CHECK: %[[VAL_8:.*]] = seq.compreg.ce sym @p0_stage0_reg0 %[[VAL_0]], %[[VAL_3]], %[[VAL_7]] : i32, i1
|
||||
// CHECK: %[[VAL_9:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_10:.*]] = seq.compreg.ce sym @p0_stage0_valid %[[VAL_1]], %[[VAL_3]], %[[VAL_6]], %[[VAL_4]], %[[VAL_9]] : i1
|
||||
// CHECK: hw.output %[[VAL_8]], %[[VAL_10]] : i32, i1
|
||||
// CHECK: %[[VAL_10:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_11:.*]] = comb.xor %[[VAL_2]], %[[VAL_10]] : i1
|
||||
// CHECK: %[[VAL_12:.*]] = seq.compreg.ce sym @p0_stage1_enable %[[VAL_7]], %[[VAL_3]], %[[VAL_11]], %[[VAL_4]], %[[VAL_9]] : i1, i1
|
||||
// CHECK: %[[VAL_13:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_14:.*]] = comb.xor %[[VAL_2]], %[[VAL_13]] : i1
|
||||
// CHECK: %[[VAL_15:.*]] = comb.and %[[VAL_12]], %[[VAL_14]]
|
||||
// CHECK: hw.output %[[VAL_8]], %[[VAL_15]] : i32, i1
|
||||
// CHECK: }
|
||||
hw.module @testWithStall(%arg0: i32, %go: i1, %stall : i1, %clk: i1, %rst: i1) -> (out0: i32, out1: i1) {
|
||||
%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) stall(%s = %stall) clock(%c = %clk) reset(%r = %rst) go(%g = %go) -> (out: i32) {
|
||||
|
|
@ -225,3 +230,51 @@ hw.module @testWithStall(%arg0: i32, %go: i1, %stall : i1, %clk: i1, %rst: i1) -
|
|||
}
|
||||
hw.output %0#0, %0#1 : i32, i1
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
// CHECK-LABEL: hw.module @testStallability(
|
||||
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i1, %[[VAL_2:.*]]: i1, %[[VAL_3:.*]]: i1, %[[VAL_4:.*]]: i1) -> (out: i32) {
|
||||
// CHECK: %[[VAL_5:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_6:.*]] = comb.xor %[[VAL_4]], %[[VAL_5]] : i1
|
||||
// CHECK: %[[VAL_7:.*]] = comb.and %[[VAL_1]], %[[VAL_6]]
|
||||
// CHECK: %[[VAL_8:.*]] = seq.compreg.ce sym @MyPipeline_a0 %[[VAL_0]], %[[VAL_2]], %[[VAL_7]] : i32, i1
|
||||
// CHECK: %[[VAL_9:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_10:.*]] = seq.compreg sym @MyPipeline_stage1_enable %[[VAL_7]], %[[VAL_2]], %[[VAL_3]], %[[VAL_9]] : i1, i1
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg.ce sym @MyPipeline_a0 %[[VAL_8]], %[[VAL_2]], %[[VAL_10]] {name = "MyPipeline_a0"} : i32, i1
|
||||
// CHECK: %[[VAL_12:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_13:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_14:.*]] = comb.xor %[[VAL_4]], %[[VAL_13]] : i1
|
||||
// CHECK: %[[VAL_15:.*]] = comb.or %[[VAL_10]], %[[VAL_14]] : i1
|
||||
// CHECK: %[[VAL_16:.*]] = seq.compreg.ce sym @MyPipeline_stage2_enable %[[VAL_10]], %[[VAL_2]], %[[VAL_15]], %[[VAL_3]], %[[VAL_12]] : i1, i1
|
||||
// CHECK: %[[VAL_17:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_18:.*]] = comb.xor %[[VAL_4]], %[[VAL_17]] : i1
|
||||
// CHECK: %[[VAL_19:.*]] = comb.or %[[VAL_10]], %[[VAL_18]] : i1
|
||||
// CHECK: %[[VAL_20:.*]] = comb.and %[[VAL_16]], %[[VAL_19]]
|
||||
// CHECK: %[[VAL_21:.*]] = seq.compreg.ce sym @MyPipeline_a0 %[[VAL_11]], %[[VAL_2]], %[[VAL_20]] {name = "MyPipeline_a0"} : i32, i1
|
||||
// CHECK: %[[VAL_22:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_23:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_24:.*]] = comb.xor %[[VAL_4]], %[[VAL_23]] : i1
|
||||
// CHECK: %[[VAL_25:.*]] = comb.or %[[VAL_10]], %[[VAL_24]] : i1
|
||||
// CHECK: %[[VAL_26:.*]] = seq.compreg.ce sym @MyPipeline_stage3_enable %[[VAL_20]], %[[VAL_2]], %[[VAL_25]], %[[VAL_3]], %[[VAL_22]] : i1, i1
|
||||
// CHECK: %[[VAL_27:.*]] = hw.constant true
|
||||
// CHECK: %[[VAL_28:.*]] = comb.xor %[[VAL_4]], %[[VAL_27]] : i1
|
||||
// CHECK: %[[VAL_29:.*]] = comb.or %[[VAL_10]], %[[VAL_28]] : i1
|
||||
// CHECK: %[[VAL_30:.*]] = comb.and %[[VAL_26]], %[[VAL_29]]
|
||||
// CHECK: hw.output %[[VAL_21]] : i32
|
||||
// CHECK: }
|
||||
|
||||
hw.module @testStallability(%arg0: i32, %go: i1, %clk: i1, %rst: i1, %stall: i1) -> (out: i32) {
|
||||
%out, %done = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0)
|
||||
stall(%s = %stall) clock(%c = %clk) reset(%r = %rst) go(%g = %go)
|
||||
{stallability = [true, false, true]} -> (out : i32) {
|
||||
pipeline.stage ^bb1 regs("a0" = %a0 : i32)
|
||||
^bb1(%a0_0: i32, %s1_enable: i1): // pred: ^bb0
|
||||
pipeline.stage ^bb2 regs("a0" = %a0_0 : i32)
|
||||
^bb2(%a0_1: i32, %s2_enable: i1): // pred: ^bb1
|
||||
pipeline.stage ^bb3 regs("a0" = %a0_1 : i32)
|
||||
^bb3(%a0_2: i32, %s3_enable: i1): // pred: ^bb2
|
||||
pipeline.return %a0_2 : i32
|
||||
}
|
||||
hw.output %out : i32
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_6]] : i32
|
||||
// CHECK: %[[VAL_8:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[VAL_6]] : i32
|
||||
// CHECK: %[[VAL_9:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_10:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_9]] : i1
|
||||
// CHECK: %[[VAL_10:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_9]] : i1
|
||||
// CHECK: %[[VAL_11:.*]] = comb.add %[[VAL_7]], %[[VAL_8]] : i32
|
||||
// CHECK: hw.output %[[VAL_11]], %[[VAL_10]] : i32, i1
|
||||
// CHECK: }
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
// CHECK: %[[VAL_8:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_9:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[VAL_3]] : i32
|
||||
// CHECK: %[[VAL_10:.*]] = hw.constant false
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_10]] : i1
|
||||
// CHECK: %[[VAL_11:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_10]] : i1
|
||||
// CHECK: %[[VAL_12:.*]] = comb.add %[[VAL_8]], %[[VAL_9]] : i32
|
||||
// CHECK: hw.output %[[VAL_12]], %[[VAL_11]] : i32, i1
|
||||
// CHECK: }
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
// CGATE: %[[VAL_11:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_10]] : i32
|
||||
// CGATE: %[[VAL_12:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[VAL_8]] : i32
|
||||
// CGATE: %[[VAL_13:.*]] = hw.constant false
|
||||
// CGATE: %[[VAL_14:.*]] = seq.compreg sym @p0_stage0_valid %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_13]] : i1
|
||||
// CGATE: %[[VAL_14:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[VAL_3]], %[[VAL_4]], %[[VAL_13]] : i1
|
||||
// CGATE: %[[VAL_15:.*]] = comb.add %[[VAL_11]], %[[VAL_12]] : i32
|
||||
// CGATE: hw.output %[[VAL_15]], %[[VAL_14]] : i32, i1
|
||||
// CGATE: }
|
||||
|
|
|
|||
|
|
@ -180,3 +180,39 @@ hw.module @invalid_clock_gate(%arg : i32, %go : i1, %clk : i1, %rst : i1) -> ()
|
|||
}
|
||||
hw.output
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
hw.module @noStallSignalWithStallability(%arg0 : i32, %go : i1, %clk : i1, %rst : i1) -> (out: i32) {
|
||||
// expected-error @+1 {{'pipeline.scheduled' op cannot specify stallability without a stall signal.}}
|
||||
%0:2 = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0) clock(%c = %clk) reset(%r = %rst) go(%g = %go)
|
||||
{stallability = [true, false, true]}
|
||||
-> (out: i32) {
|
||||
pipeline.stage ^bb1
|
||||
^bb1(%s1_enable : i1):
|
||||
pipeline.stage ^bb2
|
||||
^bb2(%s2_enable : i1):
|
||||
pipeline.stage ^bb3
|
||||
^bb3(%s3_enable : i1):
|
||||
pipeline.return %a0 : i32
|
||||
}
|
||||
hw.output %0 : i32
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
hw.module @incorrectStallabilitySize(%arg0 : i32, %go : i1, %clk : i1, %rst : i1, %stall : i1) -> (out: i32) {
|
||||
// expected-error @+1 {{'pipeline.scheduled' op stallability array must be the same length as the number of stages. Pipeline has 3 stages but array had 2 elements.}}
|
||||
%0:2 = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0) stall(%s = %stall) clock(%c = %clk) reset(%r = %rst) go(%g = %go)
|
||||
{stallability = [true, false]}
|
||||
-> (out: i32) {
|
||||
pipeline.stage ^bb1
|
||||
^bb1(%s1_enable : i1):
|
||||
pipeline.stage ^bb2
|
||||
^bb2(%s2_enable : i1):
|
||||
pipeline.stage ^bb3
|
||||
^bb3(%s3_enable : i1):
|
||||
pipeline.return %a0 : i32
|
||||
}
|
||||
hw.output %0 : i32
|
||||
}
|
||||
|
|
|
|||
|
|
@ -156,3 +156,20 @@ hw.module @withNames(%arg0 : i32, %arg1 : i32, %go : i1, %clk : i1, %rst : i1) -
|
|||
}
|
||||
hw.output %0 : i32
|
||||
}
|
||||
|
||||
// CHECK-LABEL: hw.module @withStallability(
|
||||
// CHECK: %out, %done = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0) stall(%s = %stall) clock(%c = %clk) reset(%r = %rst) go(%g = %go) {stallability = [true, false, true]} -> (out : i32)
|
||||
hw.module @withStallability(%arg0 : i32, %go : i1, %clk : i1, %rst : i1, %stall : i1) -> (out: i32) {
|
||||
%0:2 = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0) stall(%s = %stall) clock(%c = %clk) reset(%r = %rst) go(%g = %go)
|
||||
{stallability = [true, false, true]}
|
||||
-> (out: i32) {
|
||||
pipeline.stage ^bb1
|
||||
^bb1(%s1_enable : i1):
|
||||
pipeline.stage ^bb2
|
||||
^bb2(%s2_enable : i1):
|
||||
pipeline.stage ^bb3
|
||||
^bb3(%s3_enable : i1):
|
||||
pipeline.return %a0 : i32
|
||||
}
|
||||
hw.output %0 : i32
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue