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[PrettifyVerilog] Fix a crash caused by comparing different width of APInt (#4031) 

This fixes https://github.com/llvm/circt/issues/4030. The crash was caused by comparing different width of APInt so this PR fixes the issue by checking types before comparing APInt.
This commit is contained in:
Hideto Ueno 2022-09-30 21:02:35 +09:00 committed by GitHub
parent 275e4d75dd
commit f1bda70bb0
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2 changed files with 15 additions and 1 deletions
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2
lib/Dialect/SV/Transforms/PrettifyVerilog.cpp
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@ -101,7 +101,7 @@ static bool isSelfWrite(Value dst, Value src) {
})
.Case<hw::ArrayGetOp>([&](auto get) {
auto toGet = dyn_cast<sv::ArrayIndexInOutOp>(dstOp);
if (!toGet)
if (!toGet || toGet.getIndex().getType() != get.getIndex().getType())
return false;
auto toIdx = getInt(toGet.getIndex());
auto fromIdx = getInt(get.getIndex());

14
test/Dialect/SV/prettify-verilog.mlir
View File

@ -584,3 +584,17 @@ hw.module private @SelfConnect(%clock: i1, %reset: i1) -> () {
//VERILOG: always @(posedge clock)
//VERILOG: r <= r;
}
// CHECK-LABEL: Issue4030
hw.module @Issue4030(%a: i1, %clock: i1, %in1: !hw.array<2xi1>) -> (b: !hw.array<5xi1>) {
%c0_i3 = hw.constant 0 : i3
%false = hw.constant false
%0 = hw.array_get %in1[%false] : !hw.array<2xi1>, i1
%r = sv.reg : !hw.inout<array<5xi1>>
%1 = sv.array_index_inout %r[%c0_i3] : !hw.inout<array<5xi1>>, i3
%2 = sv.read_inout %r : !hw.inout<array<5xi1>>
sv.always posedge %clock {
sv.passign %1, %0 : i1
}
hw.output %2 : !hw.array<5xi1>
}