mirror of https://github.com/llvm/circt.git
[FIRRTL] Whitespace cleanup, NFC
Cleanup miscellaneous whitespace issues. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit is contained in:
Schuyler Eldridge
parent
194dc2fdfe
commit
f0db1d60c6
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@ -119,7 +119,7 @@ def GetWidthAsIntAttr : NativeCodeCall<
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"$0.getType().cast<FIRRTLType>().getBitWidthOrSentinel())">;
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////////////////////////////////////////////////////////////////////////////////
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// Drop name if no symbol (DontTouch application) and name is a stylized
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// Drop name if no symbol (DontTouch application) and name is a stylized
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// temporary name
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////////////////////////////////////////////////////////////////////////////////
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@ -153,7 +153,7 @@ def FMemModuleOp : FIRRTLOp<"memmodule",
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The "firrtl.memmodule" operation represents an external reference to a
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memory module. See the "firrtl.mem" op for a deeper explantation of the
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parameters.
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A "firrtl.mem" operation is typically lowered to this operation when they
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are not directly lowered to registers by the compiler.
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}];
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@ -190,7 +190,7 @@ def FMemModuleOp : FIRRTLOp<"memmodule",
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}
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def NonLocalAnchor : FIRRTLOp<"nla",
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[IsolatedFromAbove, Symbol,
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[IsolatedFromAbove, Symbol,
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DeclareOpInterfaceMethods<SymbolUserOpInterface>,
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HasParent<"CircuitOp">]> {
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let summary = "Anchor for non-local annotations";
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@ -220,7 +220,7 @@ def NonLocalAnchor : FIRRTLOp<"nla",
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/// Replace the oldMod module with newMod module in the namepath of the NLA.
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/// Since the module is being updated, the symbols inside the module should
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/// also be renamed. Use the rename Map to update the corresponding
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/// also be renamed. Use the rename Map to update the corresponding
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/// inner_sym names in the namepath. Return true if any update is made.
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bool updateModuleAndInnerRef(StringAttr oldMod, StringAttr newMod,
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const llvm::DenseMap<StringAttr, StringAttr> &innerSymRenameMap);
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@ -3208,7 +3208,6 @@ LogicalResult HWStructCastOp::verify() {
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}
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LogicalResult BitCastOp::verify() {
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auto inTypeBits = getBitWidth(getOperand().getType().cast<FIRRTLType>());
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auto resTypeBits = getBitWidth(getType());
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if (inTypeBits.hasValue() && resTypeBits.hasValue()) {
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@ -3285,7 +3284,6 @@ static void printElidePortAnnotations(OpAsmPrinter &p, Operation *op,
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static ParseResult parseImplicitSSAName(OpAsmParser &parser,
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NamedAttrList &resultAttrs) {
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if (parseElideAnnotations(parser, resultAttrs))
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return failure();
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@ -3356,7 +3354,6 @@ static ParseResult parseElideEmptyName(OpAsmParser &p,
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static void printElideEmptyName(OpAsmPrinter &p, Operation *op,
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DictionaryAttr attr,
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ArrayRef<StringRef> extraElides = {}) {
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SmallVector<StringRef> elides(extraElides.begin(), extraElides.end());
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if (op->getAttrOfType<StringAttr>("name").getValue().empty())
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elides.push_back("name");
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@ -3616,7 +3613,6 @@ bool NonLocalAnchor::isComponent() { return (bool)ref(); }
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// 7. The last element of the namepath can also be a module symbol.
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LogicalResult
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NonLocalAnchor::verifySymbolUses(mlir::SymbolTableCollection &symtblC) {
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Operation *op = *this;
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CircuitOp cop = op->getParentOfType<CircuitOp>();
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auto &symtbl = symtblC.getSymbolTable(cop);
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@ -3731,7 +3727,6 @@ ParseResult NonLocalAnchor::parse(OpAsmParser &parser, OperationState &result) {
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static void genericAsmResultNames(Operation *op,
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OpAsmSetValueNameFn setNameFn) {
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// Many firrtl dialect operations have an optional 'name' attribute. If
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// present, use it.
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if (op->getNumResults() == 1)
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@ -663,7 +663,7 @@ firrtl.circuit "FixPath" attributes
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// CHECK-LABEL: firrtl.circuit "FixPath"
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// CHECK: firrtl.module @FixPath
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// CHECK: firrtl.instance d @D()
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// CHECK: sv.verbatim
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// CHECK: sv.verbatim
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// CHECK-SAME: name\22: \22dutInstance\22,\0A
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// CHECK-SAME: OMMemberInstanceTarget:~FixPath|{{[{][{]0[}][}]}}/{{[{][{]1[}][}]}}:{{[{][{]2[}][}]}}
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// CHECK-SAME: name\22: \22pwm\22,\0A
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@ -671,6 +671,6 @@ firrtl.circuit "FixPath" attributes
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// CHECK-SAME: name\22: \22power\22,\0A
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// CHECK-SAME: value\22: \22OMMemberInstanceTarget:~C|{{[{][{]2[}][}]}}/{{[{][{]4[}][}]}}:{{[{][{]5[}][}]}}
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// CHECK-SAME: name\22: \22d\22,\0A
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// CHECK-SAME: value\22: \22OMMemberInstanceTarget:~FixPath|{{[{][{]5[}][}]}}\22\0A
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// CHECK-SAME: value\22: \22OMMemberInstanceTarget:~FixPath|{{[{][{]5[}][}]}}\22\0A
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// CHECK-SAME: {output_file = #hw.output_file<"omir.json", excludeFromFileList>, symbols = [@FixPath, #hw.innerNameRef<@FixPath::@c>, @C, #hw.innerNameRef<@C::@in>, #hw.innerNameRef<@C::@cd>, @D]}
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}
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@ -675,7 +675,7 @@ firrtl.nla @NLA1 []
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firrtl.nla @NLA2 [@LowerToBind::@s1]
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firrtl.module @InstanceLowerToBind() {}
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firrtl.module @LowerToBind() {
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firrtl.instance foo sym @s1 {lowerToBind = true, annotations = [{circt.nonlocal = @NLA2, class = "circt.test", nl = "nl"}]} @InstanceLowerToBind()
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firrtl.instance foo sym @s1 {lowerToBind = true, annotations = [{circt.nonlocal = @NLA2, class = "circt.test", nl = "nl"}]} @InstanceLowerToBind()
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}
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}
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@ -343,7 +343,7 @@ firrtl.circuit "GCTDataMemTapsPrefix" {
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// CHECK: firrtl.module @Baz()
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// CHECK-SAME: annotations = [{circt.nonlocal = @nla_1, class = "nla_1"}, {circt.nonlocal = @nla_3, class = "nla_3"}]
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// CHECK: %mem_MPORT_en = firrtl.wire sym @s1 : !firrtl.uint<1>
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}
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// Test that NonLocalAnchors are properly updated with memmodules.
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@ -5,7 +5,7 @@ firrtl.circuit "MyModule" {
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firrtl.module @mod() { }
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firrtl.extmodule @extmod()
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firrtl.memmodule @memmod () attributes {
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depth = 16 : ui64, dataWidth = 1 : ui32, extraPorts = [],
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depth = 16 : ui64, dataWidth = 1 : ui32, extraPorts = [],
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maskBits = 0 : ui32, numReadPorts = 0 : ui32, numWritePorts = 0 : ui32,
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numReadWritePorts = 0 : ui32, readLatency = 0 : ui32,
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writeLatency = 1 : ui32}
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@ -177,7 +177,7 @@ firrtl.module @VerbatimExpr() {
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// CHECK: firrtl.instance foo sym @s1 {lowerToBind = true} @InstanceLowerToBind()
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firrtl.module @InstanceLowerToBind() {}
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firrtl.module @LowerToBind() {
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firrtl.instance foo sym @s1 {lowerToBind = true} @InstanceLowerToBind()
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firrtl.instance foo sym @s1 {lowerToBind = true} @InstanceLowerToBind()
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}
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// CHECK-LABEL: @ProbeTest
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