diff --git a/include/circt/Dialect/Comb/Combinational.td b/include/circt/Dialect/Comb/Combinational.td
index 67ab1359e1..9ef3796119 100644
--- a/include/circt/Dialect/Comb/Combinational.td
+++ b/include/circt/Dialect/Comb/Combinational.td
@@ -52,7 +52,7 @@ class UTVariadicOp<string mnemonic, list<OpTrait> traits = []> :
   let assemblyFormat = "$inputs attr-dict `:` type($result)";
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$lhs, "Value":$rhs), [{
+    OpBuilder<(ins "Value":$lhs, "Value":$rhs), [{
       return build($_builder, $_state, lhs.getType(),
                    ValueRange{lhs, rhs}, ArrayRef<NamedAttribute>{});
     }]>
@@ -135,7 +135,7 @@ def ICmpOp : CombOp<"icmp", [NoSideEffect, SameTypeOperands]> {
   let hasCanonicalizer = true;
 
   let builders = [
-    OpBuilderDAG<(ins "ICmpPredicate":$pred, "Value":$lhs, "Value":$rhs), [{
+    OpBuilder<(ins "ICmpPredicate":$pred, "Value":$lhs, "Value":$rhs), [{
       return build($_builder, $_state, $_builder.getI1Type(), pred, lhs, rhs);
     }]>
   ];
@@ -208,8 +208,8 @@ def ConcatOp : VariadicOp<"concat"> {
   let hasCanonicalizer = true;
 
   let builders = [
-    OpBuilderDAG<(ins "ValueRange":$inputs)>,
-    OpBuilderDAG<(ins "Value":$lhs, "Value":$rhs), [{
+    OpBuilder<(ins "ValueRange":$inputs)>,
+    OpBuilder<(ins "Value":$lhs, "Value":$rhs), [{
       return build($_builder, $_state, ValueRange{lhs, rhs});
     }]>
   ];
@@ -236,7 +236,7 @@ def MuxOp : CombOp<"mux",
   let hasCanonicalizer = true;
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$cond, "Value":$trueValue, "Value":$falseValue),
+    OpBuilder<(ins "Value":$cond, "Value":$trueValue, "Value":$falseValue),
     [{
       assert(trueValue.getType() == falseValue.getType() &&
              "mux requires matching true/false value types");
diff --git a/include/circt/Dialect/ESI/ESIPorts.td b/include/circt/Dialect/ESI/ESIPorts.td
index b235c7cb0c..209929b1ec 100644
--- a/include/circt/Dialect/ESI/ESIPorts.td
+++ b/include/circt/Dialect/ESI/ESIPorts.td
@@ -60,7 +60,7 @@ def WrapValidReady : ESI_Op<"wrap.vr", [NoSideEffect]> {
   let parser = [{ return ::parse$cppClass(parser, result); }];
 
   let builders = [
-    OpBuilderDAG<(ins "mlir::Value":$data, "mlir::Value":$valid)>
+    OpBuilder<(ins "mlir::Value":$data, "mlir::Value":$valid)>
   ];
 }
 
@@ -79,7 +79,7 @@ def UnwrapValidReady : ESI_Op<"unwrap.vr", [NoSideEffect]> {
   let parser = [{ return ::parse$cppClass(parser, result); }];
 
   let builders = [
-    OpBuilderDAG<(ins "mlir::Value":$inChan, "mlir::Value":$ready)>
+    OpBuilder<(ins "mlir::Value":$inChan, "mlir::Value":$ready)>
   ];
 }
 
diff --git a/include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td b/include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td
index 4528538b06..1ad3c5d330 100644
--- a/include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td
+++ b/include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td
@@ -176,7 +176,7 @@ def WireOp : FIRRTLOp<"wire", []> {
   let results = (outs FIRRTLType:$result);
 
   let builders = [
-    OpBuilderDAG<(ins "::mlir::Type":$elementType,
+    OpBuilder<(ins "::mlir::Type":$elementType,
                       CArg<"StringRef", "{}">:$name), [{
       return build($_builder, $_state, elementType,
                    $_builder.getStringAttr(name));
diff --git a/include/circt/Dialect/FIRRTL/FIRRTLExpressions.td b/include/circt/Dialect/FIRRTL/FIRRTLExpressions.td
index cf8d4bb062..90fe9836a0 100644
--- a/include/circt/Dialect/FIRRTL/FIRRTLExpressions.td
+++ b/include/circt/Dialect/FIRRTL/FIRRTLExpressions.td
@@ -27,7 +27,7 @@ def ConstantOp : FIRRTLOp<"constant", [NoSideEffect, ConstantLike,
   let assemblyFormat = "`(` $value `)` attr-dict `:` type($result)";
 
   let builders = [
-    OpBuilderDAG<(ins "IntType":$type, "const APInt &":$value)>
+    OpBuilder<(ins "IntType":$type, "const APInt &":$value)>
   ];
   let hasFolder = 1;
   let verifier = "return ::verifyConstantOp(*this);";
@@ -316,7 +316,7 @@ def BitsPrimOp : PrimOp<"bits"> {
   let hasFolder = 1;
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$input, "unsigned":$high, "unsigned":$low)>
+    OpBuilder<(ins "Value":$input, "unsigned":$high, "unsigned":$low)>
   ];
 
   let extraClassDeclaration = [{
@@ -603,7 +603,7 @@ def AsPassivePrimOp : FIRRTLOp<"asPassive", [NoSideEffect,
   let assemblyFormat = "$input attr-dict `:` type($input)";
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$input)>
+    OpBuilder<(ins "Value":$input)>
   ];
 }
 
diff --git a/include/circt/Dialect/FIRRTL/FIRRTLStatements.td b/include/circt/Dialect/FIRRTL/FIRRTLStatements.td
index ca74091834..d42d1ea07f 100644
--- a/include/circt/Dialect/FIRRTL/FIRRTLStatements.td
+++ b/include/circt/Dialect/FIRRTL/FIRRTLStatements.td
@@ -153,7 +153,7 @@ def WhenOp : FIRRTLOp<"when", [SingleBlockImplicitTerminator<"DoneOp">,
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "Value":$condition, "bool":$withElseRegion,
+    OpBuilder<(ins "Value":$condition, "bool":$withElseRegion,
                       CArg<"std::function<void()>", "{}">:$thenCtor,
                       CArg<"std::function<void()>", "{}">:$elseCtor)>
   ];
diff --git a/include/circt/Dialect/FIRRTL/FIRRTLStructure.td b/include/circt/Dialect/FIRRTL/FIRRTLStructure.td
index e85a18c0b1..14b5618e0b 100644
--- a/include/circt/Dialect/FIRRTL/FIRRTLStructure.td
+++ b/include/circt/Dialect/FIRRTL/FIRRTLStructure.td
@@ -24,7 +24,7 @@ def CircuitOp : FIRRTLOp<"circuit",
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringAttr":$name)>
+    OpBuilder<(ins "StringAttr":$name)>
   ];
 
   let extraClassDeclaration = [{
@@ -60,7 +60,7 @@ def FModuleOp : FIRRTLOp<"module",
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringAttr":$name, "ArrayRef<ModulePortInfo>":$ports)>
+    OpBuilder<(ins "StringAttr":$name, "ArrayRef<ModulePortInfo>":$ports)>
   ];
 
   let extraClassDeclaration = [{
@@ -125,7 +125,7 @@ def FExtModuleOp : FIRRTLOp<"extmodule",
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringAttr":$name,
+    OpBuilder<(ins "StringAttr":$name,
                       "ArrayRef<ModulePortInfo>":$ports,
                       CArg<"StringRef", "StringRef()">:$defnamAttr)>
   ];
diff --git a/include/circt/Dialect/Handshake/HandshakeOps.td b/include/circt/Dialect/Handshake/HandshakeOps.td
index 5e40242418..b611f19cc4 100644
--- a/include/circt/Dialect/Handshake/HandshakeOps.td
+++ b/include/circt/Dialect/Handshake/HandshakeOps.td
@@ -60,7 +60,7 @@ def FuncOp : Op<Handshake_Dialect, "func", [
   let skipDefaultBuilders = 1;
 
   let builders =
-       [OpBuilderDAG<(ins "StringRef":$name, "FunctionType":$type,
+       [OpBuilder<(ins "StringRef":$name, "FunctionType":$type,
                       CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs,
                       CArg<"ArrayRef<NamedAttrList>", "{}">:$argAttrs),
                       [{
@@ -176,19 +176,19 @@ def InstanceOp : Handshake_Op<"instance", [CallOpInterface]> {
   let arguments = (ins FlatSymbolRefAttr:$module, Variadic<AnyType>:$operands);
   let results = (outs Variadic<AnyType>);
 
-  let builders = [OpBuilderDAG<
+  let builders = [OpBuilder<
     (ins "FuncOp":$module, CArg<"ValueRange", "{}">:$operands), [{
       $_state.addOperands(operands);
       $_state.addAttribute("module", $_builder.getSymbolRefAttr(module));
       $_state.addTypes(module.getType().getResults());
-  }]>, OpBuilderDAG<
-    (ins "SymbolRefAttr":$module, "ArrayRef<Type>":$results,
+  }]>, OpBuilder<
+    (ins "SymbolRefAttr":$module, "TypeRange":$results,
      CArg<"ValueRange", "{}">:$operands), [{
       $_state.addOperands(operands);
       $_state.addAttribute("module", module);
       $_state.addTypes(results);
-  }]>, OpBuilderDAG<
-    (ins "StringRef":$module, "ArrayRef<Type>":$results,
+  }]>, OpBuilder<
+    (ins "StringRef":$module, "TypeRange":$results,
      CArg<"ValueRange", "{}">:$operands), [{
       build($_builder, $_state, $_builder.getSymbolRefAttr(module), results,
             operands);
@@ -234,7 +234,7 @@ def ReturnOp : Handshake_Op<"return", [Terminator]> {
 
   let skipDefaultBuilders = 1;
 
-  let builders = [OpBuilderDAG<(ins "ArrayRef<Value>":$operands)>];
+  let builders = [OpBuilder<(ins "ArrayRef<Value>":$operands)>];
 
   let printer = "return ::print(p, *this);";
   let verifier = "return ::verify(*this);";
@@ -285,7 +285,7 @@ def ForkOp : Handshake_Op<"fork", [
 
   let hasCanonicalizer = 1;
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$operand, "int":$outputs)>];
+  let builders = [OpBuilder<(ins "Value":$operand, "int":$outputs)>];
 
   let extraClassDeclaration = [{
     bool isControl() { return (*this)->getAttrOfType<BoolAttr>("control").getValue(); }
@@ -304,7 +304,7 @@ def LazyForkOp : Handshake_Op<"lazy_fork", [NoSideEffect]> {
   let results = (outs Variadic<AnyType>);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$operand, "int":$outputs)>];
+  let builders = [OpBuilder<(ins "Value":$operand, "int":$outputs)>];
 
   let extraClassDeclaration = [{
     bool isControl() {  return (*this)->getAttrOfType<BoolAttr>("control").getValue(); }
@@ -327,7 +327,7 @@ def MergeOp : Handshake_Op<"merge", [
   let results = (outs AnyType);
 
   let hasCanonicalizer = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$operand, "int":$inputs)>];
+  let builders = [OpBuilder<(ins "Value":$operand, "int":$inputs)>];
 }
 
 def MuxOp : Handshake_Op<"mux", [
@@ -349,7 +349,7 @@ def MuxOp : Handshake_Op<"mux", [
 							  Variadic<AnyType> : $dataOperands);
   let results = (outs AnyType);
 
-  let builders = [OpBuilderDAG<(ins "Value":$operand, "int":$inputs)>];
+  let builders = [OpBuilder<(ins "Value":$operand, "int":$inputs)>];
   let verifier = "return ::verify(*this);";
 }
 
@@ -371,7 +371,7 @@ def ControlMergeOp : Handshake_Op<"control_merge", [
   let results = (outs Variadic<AnyType>);
 
   let hasCanonicalizer = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$operand, "int":$inputs)>];
+  let builders = [OpBuilder<(ins "Value":$operand, "int":$inputs)>];
 
   let extraClassDeclaration = [{
     bool isControl() {
@@ -396,7 +396,7 @@ def BranchOp : Handshake_Op<"branch", [
   let results = (outs AnyType : $dataResult);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$dataOperand)>];
+  let builders = [OpBuilder<(ins "Value":$dataOperand)>];
 
   let hasCanonicalizer = 1;
   let extraClassDeclaration = [{
@@ -422,7 +422,7 @@ def ConditionalBranchOp : Handshake_Op<"conditional_branch", [
   let results = (outs AnyType : $trueResult,
                       AnyType : $falseResult);
 
-  let builders = [OpBuilderDAG<(ins "Value":$condOperand, "Value":$dataOperand)>];
+  let builders = [OpBuilder<(ins "Value":$condOperand, "Value":$dataOperand)>];
 
   let extraClassDeclaration = [{
     // These are the indices into the dests list.
@@ -449,7 +449,7 @@ def SinkOp : Handshake_Op<"sink", [
   let arguments = (ins AnyType);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$operand)>];
+  let builders = [OpBuilder<(ins "Value":$operand)>];
 }
 
 def SourceOp : Handshake_Op<"source", [NoSideEffect]> {
@@ -489,7 +489,7 @@ def ConstantOp : Handshake_Op<"constant", [
   let results = (outs AnyType);
 
   // let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "Attribute":$value, "Value":$operand)>];
+  let builders = [OpBuilder<(ins "Attribute":$value, "Value":$operand)>];
 
   let extraClassDeclaration = [{
     Attribute getValue() { return (*this)->getAttr("value"); }
@@ -508,7 +508,7 @@ def EndOp
   let arguments = (ins AnyType : $control, Variadic<AnyType>);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "Value":$operand)>];
+  let builders = [OpBuilder<(ins "Value":$operand)>];
 }
 
 def StartOp : Handshake_Op<"start", [
@@ -524,7 +524,7 @@ def StartOp : Handshake_Op<"start", [
   let results = (outs NoneType);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins)>];
+  let builders = [OpBuilder<(ins)>];
 }
 
 def TerminatorOp : Handshake_Op<"terminator", [Terminator]> {
@@ -538,7 +538,7 @@ def TerminatorOp : Handshake_Op<"terminator", [Terminator]> {
 
   let successors = (successor VariadicSuccessor<AnySuccessor>:$dests);
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "ArrayRef<Block *>":$successors)>];
+  let builders = [OpBuilder<(ins "ArrayRef<Block *>":$successors)>];
 }
 
 def MemRefTypeAttr : TypeAttrBase<"MemRefType", "memref type attribute">;
@@ -564,7 +564,7 @@ def MemoryOp : Handshake_Op<"memory", [
   let results = (outs Variadic<AnyType>);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(
+  let builders = [OpBuilder<(
       ins "ArrayRef<Value>":$operands, "int":$outputs, "int":$control_outputs, "bool":$lsq,
       "int":$id, "Value":$memref)>
   ];
@@ -602,7 +602,7 @@ def LoadOp
   let arguments = (ins Variadic<AnyType>, AnyType, NoneType);
   let results = (outs AnyType, Variadic<AnyType>:$addressResults);
 
-  let builders = [OpBuilderDAG<(ins "Value":$memref, "ArrayRef<Value>":$indices)>];
+  let builders = [OpBuilder<(ins "Value":$memref, "ArrayRef<Value>":$indices)>];
 }
 
 def StoreOp : Handshake_Op<"store", [
@@ -625,7 +625,7 @@ def StoreOp : Handshake_Op<"store", [
   let results = (outs AnyType, Variadic<AnyType>);
 
   let builders =
-      [OpBuilderDAG<(ins "Value":$valueToStore, "ArrayRef<Value>":$indices)>];
+      [OpBuilder<(ins "Value":$valueToStore, "ArrayRef<Value>":$indices)>];
 }
 
 def JoinOp : Handshake_Op<"join", [
@@ -641,7 +641,7 @@ def JoinOp : Handshake_Op<"join", [
   let results = (outs NoneType);
 
   let skipDefaultBuilders = 1;
-  let builders = [OpBuilderDAG<(ins "ArrayRef<Value>":$operands)>];
+  let builders = [OpBuilder<(ins "ArrayRef<Value>":$operands)>];
 }
 
 def I4 : I<4>;
diff --git a/include/circt/Dialect/LLHD/IR/LLHDDialect.h b/include/circt/Dialect/LLHD/IR/LLHDDialect.h
index f293caf1c5..b6597f2af0 100644
--- a/include/circt/Dialect/LLHD/IR/LLHDDialect.h
+++ b/include/circt/Dialect/LLHD/IR/LLHDDialect.h
@@ -117,8 +117,8 @@ public:
   /// declared at the given, potentially unknown, location. If the ArrayType
   /// defined by the arguments would be ill-formed, emit errors and return
   /// nullptr-wrapping type.
-  static ArrayType getChecked(unsigned length, Type elementType,
-                              Location location);
+  static ArrayType getChecked(function_ref<InFlightDiagnostic()> emitError,
+                              unsigned length, Type elementType);
 
   /// Verify the construction of an array type.
   static LogicalResult
diff --git a/include/circt/Dialect/RTL/RTLAggregates.td b/include/circt/Dialect/RTL/RTLAggregates.td
index cc810d56ce..895a4d3514 100644
--- a/include/circt/Dialect/RTL/RTLAggregates.td
+++ b/include/circt/Dialect/RTL/RTLAggregates.td
@@ -43,7 +43,7 @@ def ArrayCreateOp : RTLOp<"array_create", [NoSideEffect, SameTypeOperands]> {
   let parser = "return ::parse$cppClass(parser, result);";
   let builders = [
     // ArrayRef needs to contain at least one element.
-    OpBuilderDAG<(ins "ArrayRef<::mlir::Value>":$input)>
+    OpBuilder<(ins "ArrayRef<::mlir::Value>":$input)>
   ];
 }
 
@@ -71,7 +71,7 @@ def ArrayConcatOp : RTLOp<"array_concat", [NoSideEffect]> {
 
   let builders = [
     // ArrayRef needs to contain at least one element.
-    OpBuilderDAG<(ins "ArrayRef<::mlir::Value>":$inputs)>
+    OpBuilder<(ins "ArrayRef<::mlir::Value>":$inputs)>
   ];
 }
 
@@ -144,7 +144,7 @@ def ArrayGetOp : RTLOp<"array_get",
   }];
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$input, "Value":$index)>
+    OpBuilder<(ins "Value":$input, "Value":$index)>
   ];
 }
 
@@ -172,7 +172,7 @@ def StructExtractOp : RTLOp<"struct_extract", [NoSideEffect]> {
   let printer = "return ::print(p, *this);";
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$input, "StructType::FieldInfo":$field)>
+    OpBuilder<(ins "Value":$input, "StructType::FieldInfo":$field)>
   ];
 }
 
@@ -220,13 +220,13 @@ def ConstantOp
   let builders = [
     /// Build a ConstantOp from an APInt, infering the result type from the
     /// width of the APInt.
-    OpBuilderDAG<(ins "const APInt &":$value)>,
+    OpBuilder<(ins "const APInt &":$value)>,
 
     /// This builder allows construction of small signed integers like 0, 1, -1
     /// matching a specified MLIR IntegerType.  This shouldn't be used for
     /// general constant folding because it only works with values that can be
     /// expressed in an int64_t.  Use APInt's instead.
-    OpBuilderDAG<(ins "Type":$type, "int64_t":$value)>
+    OpBuilder<(ins "Type":$type, "int64_t":$value)>
   ];
   let extraClassDeclaration = [{
     APInt getValue() {
diff --git a/include/circt/Dialect/RTL/RTLStructure.td b/include/circt/Dialect/RTL/RTLStructure.td
index 65a330fe4c..90ed3c1fdc 100644
--- a/include/circt/Dialect/RTL/RTLStructure.td
+++ b/include/circt/Dialect/RTL/RTLStructure.td
@@ -25,7 +25,7 @@ def RTLModuleOp : RTLOp<"module",
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringAttr":$name, "ArrayRef<ModulePortInfo>":$ports)>
+    OpBuilder<(ins "StringAttr":$name, "ArrayRef<ModulePortInfo>":$ports)>
   ];
 
   let extraClassDeclaration = [{
@@ -100,7 +100,7 @@ def RTLModuleExternOp : RTLOp<"module.extern",
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringAttr":$name,
+    OpBuilder<(ins "StringAttr":$name,
                       "ArrayRef<ModulePortInfo>":$ports,
                       CArg<"StringRef", "StringRef()">:$verilogName)>
   ];
@@ -198,7 +198,7 @@ def OutputOp : RTLOp<"output", [Terminator, HasParent<"RTLModuleOp">,
   let arguments = (ins Variadic<AnyType>:$operands);
 
   let builders = [
-    OpBuilderDAG<(ins), "build($_builder, $_state, llvm::None);">
+    OpBuilder<(ins), "build($_builder, $_state, llvm::None);">
   ];
 
   let assemblyFormat = "attr-dict ($operands^ `:` type($operands))?";
diff --git a/include/circt/Dialect/RTL/RTLTypes.td b/include/circt/Dialect/RTL/RTLTypes.td
index 72f9876454..9f6d9ebed2 100644
--- a/include/circt/Dialect/RTL/RTLTypes.td
+++ b/include/circt/Dialect/RTL/RTLTypes.td
@@ -49,7 +49,7 @@ def ArrayType : RTLType<"Array"> {
 
   let mnemonic = "array";
   let parameters = (ins "::mlir::Type":$elementType, "size_t":$size);
-  let genVerifyInvariantsDecl = 1;
+  let genVerifyDecl = 1;
 
   let extraClassDeclaration = [{
     static ArrayType get(Type elementType, size_t size) {
@@ -68,7 +68,7 @@ def UnpackedArrayType : RTLType<"UnpackedArray"> {
 
   let mnemonic = "uarray";
   let parameters = (ins "::mlir::Type":$elementType, "size_t":$size);
-  let genVerifyInvariantsDecl = 1;
+  let genVerifyDecl = 1;
 
   let extraClassDeclaration = [{
     static UnpackedArrayType get(Type elementType, size_t size) {
@@ -87,7 +87,7 @@ def InOutType : RTLType<"InOut"> {
 
   let mnemonic = "inout";
   let parameters = (ins "::mlir::Type":$elementType);
-  let genVerifyInvariantsDecl = 1;
+  let genVerifyDecl = 1;
 
   let extraClassDeclaration = [{
     static InOutType get(Type elementType) {
diff --git a/include/circt/Dialect/SV/SVInOutOps.td b/include/circt/Dialect/SV/SVInOutOps.td
index 50778b50f3..6c72d6db04 100644
--- a/include/circt/Dialect/SV/SVInOutOps.td
+++ b/include/circt/Dialect/SV/SVInOutOps.td
@@ -39,9 +39,9 @@ def WireOp : SVOp<"wire", [DeclareOpInterfaceMethods<OpAsmOpInterface>,
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "::mlir::Type":$elementType,
+    OpBuilder<(ins "::mlir::Type":$elementType,
                       CArg<"StringAttr", "StringAttr()">:$name)>,
-    OpBuilderDAG<(ins "::mlir::Type":$elementType, CArg<"StringRef">:$name), [{
+    OpBuilder<(ins "::mlir::Type":$elementType, CArg<"StringRef">:$name), [{
       return build($_builder, $_state, elementType,
                    $_builder.getStringAttr(name));
     }]>
@@ -69,7 +69,7 @@ def RegOp : SVOp<"reg", [DeclareOpInterfaceMethods<OpAsmOpInterface>]> {
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "::mlir::Type":$elementType,
+    OpBuilder<(ins "::mlir::Type":$elementType,
                       CArg<"StringAttr", "StringAttr()">:$name)>
   ];
 
@@ -93,7 +93,7 @@ def ReadInOutOp
   let results = (outs RTLValueType:$result);
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$input)>
+    OpBuilder<(ins "Value":$input)>
   ];
 
   let assemblyFormat = "$input attr-dict `:` type($input)";
@@ -119,7 +119,7 @@ def ArrayIndexInOutOp
   let results = (outs InOutType:$result);
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$input, "Value":$index)>
+    OpBuilder<(ins "Value":$input, "Value":$index)>
   ];
 
   let assemblyFormat =
diff --git a/include/circt/Dialect/SV/SVStatements.td b/include/circt/Dialect/SV/SVStatements.td
index 38ea2851a7..f17977404d 100644
--- a/include/circt/Dialect/SV/SVStatements.td
+++ b/include/circt/Dialect/SV/SVStatements.td
@@ -35,10 +35,10 @@ def IfDefOp : SVOp<"ifdef", [HasRegionTerminator, NoRegionArguments,
   // implicitly installed.
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringRef":$cond,
+    OpBuilder<(ins "StringRef":$cond,
                       CArg<"std::function<void()>", "{}">:$thenCtor,
                       CArg<"std::function<void()>", "{}">:$elseCtor)>,
-    OpBuilderDAG<(ins "StringAttr":$cond,
+    OpBuilder<(ins "StringAttr":$cond,
                       CArg<"std::function<void()>", "{}">:$thenCtor,
                       CArg<"std::function<void()>", "{}">:$elseCtor)>
   ];
@@ -78,7 +78,7 @@ def IfDefProceduralOp
   // implicitly installed.
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "StringRef":$cond,
+    OpBuilder<(ins "StringRef":$cond,
                       CArg<"std::function<void()>", "{}">:$thenCtor,
                       CArg<"std::function<void()>", "{}">:$elseCtor)>
   ];
@@ -114,7 +114,7 @@ def IfOp : SVOp<"if", [HasRegionTerminator, NoRegionArguments,
   // implicitly installed.
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "Value":$cond,
+    OpBuilder<(ins "Value":$cond,
                       CArg<"std::function<void()>", "{}">:$thenCtor,
                       CArg<"std::function<void()>", "{}">:$elseCtor)>
   ];
@@ -163,7 +163,7 @@ def AlwaysOp : SVOp<"always", [HasRegionTerminator, NoRegionArguments,
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "ArrayRef<EventControl>":$event, "ArrayRef<Value>":$cond,
+    OpBuilder<(ins "ArrayRef<EventControl>":$event, "ArrayRef<Value>":$cond,
                       CArg<"std::function<void()>", "{}">:$bodyCtor)>
   ];
 
@@ -219,9 +219,9 @@ def AlwaysFFOp : SVOp<"alwaysff", [HasRegionTerminator, NoRegionArguments,
 
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins "EventControl":$clockEdge, "Value":$clock,
+    OpBuilder<(ins "EventControl":$clockEdge, "Value":$clock,
                       CArg<"std::function<void()>", "{}">:$bodyCtor)>,
-    OpBuilderDAG<(ins "EventControl":$clockEdge, "Value":$clock, 
+    OpBuilder<(ins "EventControl":$clockEdge, "Value":$clock, 
                       "ResetType":$resetStyle,
                       "EventControl":$resetEdge, "Value":$reset,
                       CArg<"std::function<void()>", "{}">:$bodyCtor,
@@ -251,7 +251,7 @@ def InitialOp : SVOp<"initial", [HasRegionTerminator, NoRegionArguments,
   // implicitly installed.
   let skipDefaultBuilders = 1;
   let builders = [
-    OpBuilderDAG<(ins CArg<"std::function<void()>", "{}">:$bodyCtor)>
+    OpBuilder<(ins CArg<"std::function<void()>", "{}">:$bodyCtor)>
   ];
 
   let extraClassDeclaration = [{
@@ -282,6 +282,7 @@ def CaseZOp : SVOp<"casez", [HasRegionTerminator, NoRegionArguments,
       case PatternOne: return '1';
       case PatternAny: return isVerilog ? '?' : 'x';
       }
+      llvm_unreachable("invalid casez PatternBit");
     }
 
     // This is provides convenient access to encode and decode a pattern.
@@ -419,7 +420,7 @@ def VerbatimOp : SVOp<"verbatim"> {
     "$string attr-dict (`(` $operands^ `)` `:` type($operands))?";
 
   let builders = [
-    OpBuilderDAG<(ins "StringRef":$string),
+    OpBuilder<(ins "StringRef":$string),
                  "build(odsBuilder, odsState, string, ValueRange{});">
   ];
 }
diff --git a/include/circt/Dialect/SV/SVTypeDecl.td b/include/circt/Dialect/SV/SVTypeDecl.td
index 223341db3c..cc86e81cd4 100644
--- a/include/circt/Dialect/SV/SVTypeDecl.td
+++ b/include/circt/Dialect/SV/SVTypeDecl.td
@@ -88,7 +88,7 @@ def InterfaceSignalOp : SVOp<"interface.signal",
   let assemblyFormat = "attr-dict $sym_name `:` $type";
 
   let builders = [
-    OpBuilderDAG<(ins "::llvm::StringRef":$name, "::mlir::Type":$type)>
+    OpBuilder<(ins "::llvm::StringRef":$name, "::mlir::Type":$type)>
   ];
 }
 
@@ -136,7 +136,7 @@ def InterfaceModportOp : SVOp<"interface.modport",
   let assemblyFormat = "attr-dict $sym_name custom<ModportStructs>($ports)";
 
   let builders = [
-    OpBuilderDAG<(ins "::llvm::StringRef":$name,
+    OpBuilder<(ins "::llvm::StringRef":$name,
                       "ArrayRef<::llvm::StringRef>":$inputs,
                       "ArrayRef<::llvm::StringRef>":$outputs)>
   ];
@@ -217,7 +217,7 @@ def GetModportOp: SVOp<"modport.get", [NoSideEffect]> {
   let verifier = "return ::verifyGetModportOp(*this);";
 
   let builders = [
-    OpBuilderDAG<(ins "Value":$value, "::llvm::StringRef":$field)>
+    OpBuilder<(ins "Value":$value, "::llvm::StringRef":$field)>
   ];
 }
 
@@ -274,7 +274,7 @@ def ReadInterfaceSignalOp : SVOp<"interface.signal.read", [NoSideEffect]> {
   }];
 
   let builders = [
-    OpBuilderDAG<(ins "::mlir::Value":$iface, "::llvm::StringRef":$signalName)>
+    OpBuilder<(ins "::mlir::Value":$iface, "::llvm::StringRef":$signalName)>
   ];
 
   let verifier = "return ::verifySignalExists(iface(), signalNameAttr());";
diff --git a/include/circt/Dialect/StaticLogic/StaticLogic.td b/include/circt/Dialect/StaticLogic/StaticLogic.td
index 3a3202a9eb..fa555bdc26 100644
--- a/include/circt/Dialect/StaticLogic/StaticLogic.td
+++ b/include/circt/Dialect/StaticLogic/StaticLogic.td
@@ -43,7 +43,7 @@ def PipelineOp : Op<StaticLogic_Dialect, "pipeline", [NoSideEffect]> {
 
   let skipDefaultBuilders = 1;
 
-  let builders = [OpBuilderDAG<(ins "ValueRange":$operands, "ValueRange":$results), [{
+  let builders = [OpBuilder<(ins "ValueRange":$operands, "ValueRange":$results), [{
     SmallVector<Type, 4> argTypes;
     for (auto value : operands)
       argTypes.push_back(value.getType());
diff --git a/lib/Conversion/HandshakeToFIRRTL/HandshakeToFIRRTL.cpp b/lib/Conversion/HandshakeToFIRRTL/HandshakeToFIRRTL.cpp
index 826fccc30f..12780c721f 100644
--- a/lib/Conversion/HandshakeToFIRRTL/HandshakeToFIRRTL.cpp
+++ b/lib/Conversion/HandshakeToFIRRTL/HandshakeToFIRRTL.cpp
@@ -59,6 +59,7 @@ static FIRRTLType getFIRRTLType(Type type) {
         case IntegerType::Signless:
           return UIntType::get(context, width);
         }
+        llvm_unreachable("invalid IntegerType");
       })
       .Case<IndexType>([&](IndexType indexType) -> FIRRTLType {
         // Currently we consider index type as 64-bits unsigned integer.
@@ -630,6 +631,7 @@ bool StdExprBuilder::visitStdExpr(CmpIOp op) {
   case CmpIPredicate::uge:
     return buildBinaryLogic<GEQPrimOp>(), true;
   }
+  llvm_unreachable("invalid CmpIOp");
 }
 
 /// Please refer to simple_addi.mlir test case.
diff --git a/lib/Conversion/StandardToHandshake/StandardToHandshake.cpp b/lib/Conversion/StandardToHandshake/StandardToHandshake.cpp
index 107447d976..0c51640221 100644
--- a/lib/Conversion/StandardToHandshake/StandardToHandshake.cpp
+++ b/lib/Conversion/StandardToHandshake/StandardToHandshake.cpp
@@ -187,7 +187,7 @@ BlockValues getBlockUses(handshake::FuncOp f) {
 
         Block *operandBlock;
 
-        if (op.getOperand(i).getKind() == Value::Kind::BlockArgument) {
+        if (op.getOperand(i).isa<BlockArgument>()) {
           // Operand is block argument, get its owner block
           operandBlock = op.getOperand(i).cast<BlockArgument>().getOwner();
         } else {
@@ -314,7 +314,7 @@ Operation *insertMerge(Block *block, Value val,
   unsigned numPredecessors = getBlockPredecessorCount(block);
 
   // Control-only path originates from StartOp
-  if (val.getKind() != Value::Kind::BlockArgument) {
+  if (!val.isa<BlockArgument>()) {
     if (isa<StartOp>(val.getDefiningOp())) {
       return rewriter.create<handshake::ControlMergeOp>(block->front().getLoc(),
                                                         val, numPredecessors);
@@ -362,7 +362,7 @@ BlockOps insertMergeOps(handshake::FuncOp f, BlockValues blockLiveIns,
 // Check if block contains operation which produces val
 bool blockHasSrcOp(Value val, Block *block) {
   // Arguments do not have an operation producer
-  if (val.getKind() == Value::Kind::BlockArgument)
+  if (val.isa<BlockArgument>())
     return false;
 
   auto *op = val.getDefiningOp();
@@ -1047,7 +1047,7 @@ Value getMemRefOperand(Value val) {
   assert(val != nullptr);
   // If memref is function argument, connect to memory through
   // its successor merge (all other arguments are connected like that)
-  if (val.getKind() == Value::Kind::BlockArgument) {
+  if (val.isa<BlockArgument>()) {
     assert(val.hasOneUse());
     for (auto &u : val.getUses()) {
       Operation *useOp = u.getOwner();
@@ -1422,7 +1422,7 @@ struct FuncOpLowering : public OpConversionPattern<mlir::FuncOp> {
 
     // Only retain those attributes that are not constructed by build.
     SmallVector<NamedAttribute, 4> attributes;
-    for (const auto &attr : funcOp.getAttrs()) {
+    for (const auto &attr : funcOp->getAttrs()) {
       if (attr.first == SymbolTable::getSymbolAttrName() ||
           attr.first == impl::getTypeAttrName())
         continue;
diff --git a/lib/Conversion/StandardToStaticLogic/StandardToStaticLogic.cpp b/lib/Conversion/StandardToStaticLogic/StandardToStaticLogic.cpp
index 68a8b9929f..c6e484edea 100644
--- a/lib/Conversion/StandardToStaticLogic/StandardToStaticLogic.cpp
+++ b/lib/Conversion/StandardToStaticLogic/StandardToStaticLogic.cpp
@@ -26,7 +26,7 @@ valueVector getPipelineArgs(Block &block) {
   for (auto &op : block) {
     if (!op.mightHaveTrait<OpTrait::IsTerminator>()) {
       for (auto operand : op.getOperands()) {
-        if (operand.getKind() == Value::Kind::BlockArgument) {
+        if (operand.isa<BlockArgument>()) {
           // Add only unique uses
           if (std::find(arguments.begin(), arguments.end(), operand) ==
               arguments.end())
diff --git a/lib/Dialect/ESI/ESIOps.cpp b/lib/Dialect/ESI/ESIOps.cpp
index 368cee94b8..5ffef3d911 100644
--- a/lib/Dialect/ESI/ESIOps.cpp
+++ b/lib/Dialect/ESI/ESIOps.cpp
@@ -60,7 +60,7 @@ static void print(OpAsmPrinter &p, ChannelBuffer &op) {
   p << "esi.buffer " << op.clk() << ", " << op.rstn() << ", " << op.input()
     << " ";
   p.printAttributeWithoutType(op.options());
-  p.printOptionalAttrDict(op.getAttrs(), /*elidedAttrs=*/{"options"});
+  p.printOptionalAttrDict(op->getAttrs(), /*elidedAttrs=*/{"options"});
   p << " : " << op.output().getType().cast<ChannelPort>().getInner();
 }
 
@@ -92,7 +92,7 @@ static ParseResult parsePipelineStage(OpAsmParser &parser,
 static void print(OpAsmPrinter &p, PipelineStage &op) {
   p << "esi.stage " << op.clk() << ", " << op.rstn() << ", " << op.input()
     << " ";
-  p.printOptionalAttrDict(op.getAttrs());
+  p.printOptionalAttrDict(op->getAttrs());
   p << " : " << op.output().getType().cast<ChannelPort>().getInner();
 }
 
@@ -123,7 +123,7 @@ static ParseResult parseWrapValidReady(OpAsmParser &parser,
 
 void print(OpAsmPrinter &p, WrapValidReady &op) {
   p << "esi.wrap.vr " << op.rawInput() << ", " << op.valid();
-  p.printOptionalAttrDict(op.getAttrs());
+  p.printOptionalAttrDict(op->getAttrs());
   p << " : " << op.chanOutput().getType().cast<ChannelPort>().getInner();
 }
 
@@ -158,7 +158,7 @@ static ParseResult parseUnwrapValidReady(OpAsmParser &parser,
 
 static void print(OpAsmPrinter &p, UnwrapValidReady &op) {
   p << "esi.unwrap.vr " << op.chanInput() << ", " << op.ready();
-  p.printOptionalAttrDict(op.getAttrs());
+  p.printOptionalAttrDict(op->getAttrs());
   p << " : " << op.rawOutput().getType();
 }
 
diff --git a/lib/Dialect/ESI/ESIPasses.cpp b/lib/Dialect/ESI/ESIPasses.cpp
index 482f479736..210930f132 100644
--- a/lib/Dialect/ESI/ESIPasses.cpp
+++ b/lib/Dialect/ESI/ESIPasses.cpp
@@ -519,7 +519,7 @@ void ESIPortsPass::updateInstance(RTLModuleExternOp mod, InstanceOp inst) {
 
   // Create the new instance!
   InstanceOp newInst = instBuilder.create<InstanceOp>(
-      newResultTypes, newOperands, inst.getAttrs());
+      newResultTypes, newOperands, inst->getAttrs());
   // Go through the old list of non-ESI result values, and replace them with the
   // new non-ESI results.
   for (size_t resNum = 0, numRes = newResults.size(); resNum < numRes;
diff --git a/lib/Dialect/ESI/ESITypes.cpp b/lib/Dialect/ESI/ESITypes.cpp
index 61a0d9bed3..f0942e3c61 100644
--- a/lib/Dialect/ESI/ESITypes.cpp
+++ b/lib/Dialect/ESI/ESITypes.cpp
@@ -76,8 +76,10 @@ Type ESIDialect::parseType(DialectAsmParser &parser) const {
   llvm::StringRef mnemonic;
   if (parser.parseKeyword(&mnemonic))
     return Type();
-  auto genType = generatedTypeParser(getContext(), parser, mnemonic);
-  if (genType != Type())
+  Type genType;
+  auto parseResult =
+      generatedTypeParser(getContext(), parser, mnemonic, genType);
+  if (parseResult.hasValue())
     return genType;
   parser.emitError(parser.getCurrentLocation(), "Could not parse esi.")
       << mnemonic << "!\n";
diff --git a/lib/Dialect/FIRRTL/FIRRTLOps.cpp b/lib/Dialect/FIRRTL/FIRRTLOps.cpp
index da851fa0da..c52af823f2 100644
--- a/lib/Dialect/FIRRTL/FIRRTLOps.cpp
+++ b/lib/Dialect/FIRRTL/FIRRTLOps.cpp
@@ -69,7 +69,7 @@ static void print(OpAsmPrinter &p, CircuitOp op) {
   p << op.getOperationName() << " ";
   p.printAttribute(op.nameAttr());
 
-  p.printOptionalAttrDictWithKeyword(op.getAttrs(), {"name"});
+  p.printOptionalAttrDictWithKeyword(op->getAttrs(), {"name"});
 
   p.printRegion(op.body(),
                 /*printEntryBlockArgs=*/false,
diff --git a/lib/Dialect/FIRRTL/Import/FIRLexer.cpp b/lib/Dialect/FIRRTL/Import/FIRLexer.cpp
index 701b23e549..6e0f44ffd5 100644
--- a/lib/Dialect/FIRRTL/Import/FIRLexer.cpp
+++ b/lib/Dialect/FIRRTL/Import/FIRLexer.cpp
@@ -118,8 +118,8 @@ Location FIRLexer::translateLocation(llvm::SMLoc loc) {
   auto lineAndColumn = sourceMgr.getLineAndColumn(loc, mainFileID);
   auto *buffer = sourceMgr.getMemoryBuffer(mainFileID);
 
-  return FileLineColLoc::get(buffer->getBufferIdentifier(), lineAndColumn.first,
-                             lineAndColumn.second, context);
+  return FileLineColLoc::get(context, buffer->getBufferIdentifier(),
+                             lineAndColumn.first, lineAndColumn.second);
 }
 
 /// Emit an error message and return a FIRToken::error token.
diff --git a/lib/Dialect/FIRRTL/Import/FIRParser.cpp b/lib/Dialect/FIRRTL/Import/FIRParser.cpp
index 8dad030529..8869bae4b1 100644
--- a/lib/Dialect/FIRRTL/Import/FIRParser.cpp
+++ b/lib/Dialect/FIRRTL/Import/FIRParser.cpp
@@ -413,8 +413,8 @@ ParseResult FIRParser::parseOptionalInfo(LocWithInfo &result,
 
     // On success, remember what we already parsed (Bar.Scala / 309:14), and
     // move on to the next chunk.
-    auto loc = FileLineColLoc::get(filename.drop_front(spaceLoc + 1), lineNo,
-                                   columnNo, getContext());
+    auto loc = FileLineColLoc::get(
+        getContext(), filename.drop_front(spaceLoc + 1), lineNo, columnNo);
     extraLocs.push_back(loc);
     filename = nextFilename;
     lineNo = nextLineNo;
@@ -423,11 +423,11 @@ ParseResult FIRParser::parseOptionalInfo(LocWithInfo &result,
   }
 
   Location resultLoc =
-      FileLineColLoc::get(filename, lineNo, columnNo, getContext());
+      FileLineColLoc::get(getContext(), filename, lineNo, columnNo);
   if (!extraLocs.empty()) {
     extraLocs.push_back(resultLoc);
     std::reverse(extraLocs.begin(), extraLocs.end());
-    resultLoc = FusedLoc::get(extraLocs, getContext());
+    resultLoc = FusedLoc::get(getContext(), extraLocs);
   }
   result.setInfoLocation(resultLoc);
 
@@ -2720,8 +2720,8 @@ OwningModuleRef circt::firrtl::importFIRRTL(SourceMgr &sourceMgr,
 
   // This is the result module we are parsing into.
   OwningModuleRef module(ModuleOp::create(
-      FileLineColLoc::get(sourceBuf->getBufferIdentifier(), /*line=*/0,
-                          /*column=*/0, context)));
+      FileLineColLoc::get(context, sourceBuf->getBufferIdentifier(), /*line=*/0,
+                          /*column=*/0)));
 
   GlobalFIRParserState state(sourceMgr, context, options);
   if (FIRCircuitParser(state, *module).parseCircuit())
diff --git a/lib/Dialect/FIRRTL/Transforms/BlackboxMemory.cpp b/lib/Dialect/FIRRTL/Transforms/BlackboxMemory.cpp
index 9fa9af9ad2..eb216024db 100644
--- a/lib/Dialect/FIRRTL/Transforms/BlackboxMemory.cpp
+++ b/lib/Dialect/FIRRTL/Transforms/BlackboxMemory.cpp
@@ -14,6 +14,7 @@
 #include "circt/Dialect/FIRRTL/FIRRTLOps.h"
 #include "circt/Dialect/FIRRTL/FIRRTLTypes.h"
 #include "circt/Dialect/FIRRTL/Passes.h"
+#include "circt/Support/LLVM.h"
 #include "mlir/IR/OperationSupport.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Hashing.h"
@@ -35,23 +36,7 @@ llvm::hash_code computeHash(MemOp op) {
   hash = llvm::hash_combine(hash, op.ruwAttr());
 
   // Result Types
-  ArrayRef<Type> resultTypes = op->getResultTypes();
-  switch (resultTypes.size()) {
-  case 0:
-    // We don't need to add anything to the hash.
-    break;
-  case 1:
-    // Add in the result type.
-    hash = llvm::hash_combine(hash, resultTypes.front());
-    break;
-  default:
-    // Use the type buffer as the hash, as we can guarantee it is the same for
-    // any given range of result types. This takes advantage of the fact the
-    // result types >1 are stored in a TupleType and uniqued.
-    hash = llvm::hash_combine(hash, resultTypes.data());
-    break;
-  }
-  return hash;
+  return llvm::hash_combine(hash, op->getResultTypes());
 }
 
 /// Compare memory operations for equivalence.  Only compares the types of the
@@ -69,26 +54,8 @@ static bool isEquivalentTo(MemOp lhs, MemOp rhs) {
   if (lhs.ruwAttr() != rhs.ruwAttr())
     return false;
   // Compare result types.  Taken from operation equivalence.
-  ArrayRef<Type> lhsResultTypes = lhs->getResultTypes();
-  ArrayRef<Type> rhsResultTypes = rhs->getResultTypes();
-  if (lhsResultTypes.size() != rhsResultTypes.size())
+  if (lhs->getResultTypes() != rhs->getResultTypes())
     return false;
-  switch (lhsResultTypes.size()) {
-  case 0:
-    break;
-  case 1:
-    // Compare the single result type.
-    if (lhsResultTypes.front() != rhsResultTypes.front())
-      return false;
-    break;
-  default:
-    // Use the type buffer for the comparison, as we can guarantee it is the
-    // same for any given range of result types. This takes advantage of the
-    // fact the result types >1 are stored in a TupleType and uniqued.
-    if (lhsResultTypes.data() != rhsResultTypes.data())
-      return false;
-    break;
-  }
   return true;
 }
 
diff --git a/lib/Dialect/LLHD/IR/LLHDDialect.cpp b/lib/Dialect/LLHD/IR/LLHDDialect.cpp
index c3059a65ee..0039c765ba 100644
--- a/lib/Dialect/LLHD/IR/LLHDDialect.cpp
+++ b/lib/Dialect/LLHD/IR/LLHDDialect.cpp
@@ -12,6 +12,7 @@
 
 #include "circt/Dialect/LLHD/IR/LLHDDialect.h"
 #include "circt/Dialect/LLHD/IR/LLHDOps.h"
+#include "circt/Support/LLVM.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/DialectImplementation.h"
 #include "mlir/Transforms/InliningUtils.h"
@@ -416,9 +417,10 @@ ArrayType ArrayType::get(unsigned length, Type elementType) {
   return Base::get(elementType.getContext(), length, elementType);
 }
 
-ArrayType ArrayType::getChecked(unsigned length, Type elementType,
-                                Location location) {
-  return Base::getChecked(location, length, elementType);
+ArrayType ArrayType::getChecked(function_ref<InFlightDiagnostic()> emitError,
+                                unsigned length, Type elementType) {
+  return Base::getChecked(emitError, elementType.getContext(), length,
+                          elementType);
 }
 
 LogicalResult ArrayType::verifyConstructionInvariants(Location loc,
diff --git a/lib/Dialect/LLHD/IR/LLHDOps.cpp b/lib/Dialect/LLHD/IR/LLHDOps.cpp
index bf7cf999fb..85f32e8ace 100644
--- a/lib/Dialect/LLHD/IR/LLHDOps.cpp
+++ b/lib/Dialect/LLHD/IR/LLHDOps.cpp
@@ -189,7 +189,7 @@ static void print(OpAsmPrinter &printer, llhd::ConstOp op) {
   // some reason. Work around by printing the attribute without type, explicitly
   // followed by the operation type
   printer.printAttributeWithoutType(op.valueAttr());
-  printer.printOptionalAttrDict(op.getAttrs(), {"value"});
+  printer.printOptionalAttrDict(op->getAttrs(), {"value"});
   printer << " : " << op.getType();
 }
 
@@ -659,7 +659,7 @@ static void print(OpAsmPrinter &printer, llhd::EntityOp op) {
   printer << " -> ";
   printArgumentList(printer, outs);
   printer.printOptionalAttrDictWithKeyword(
-      op.getAttrs(),
+      op->getAttrs(),
       /*elidedAttrs =*/{SymbolTable::getSymbolAttrName(),
                         llhd::EntityOp::getTypeAttrName(), "ins"});
   printer.printRegion(op.body(), false, false);
@@ -1092,7 +1092,7 @@ static void print(OpAsmPrinter &printer, llhd::RegOp op) {
       printer << " if " << op.getGateAt(i);
     printer << " : " << op.values()[i].getType() << ")";
   }
-  printer.printOptionalAttrDict(op.getAttrs(),
+  printer.printOptionalAttrDict(op->getAttrs(),
                                 {"modes", "gateMask", "operand_segment_sizes"});
   printer << " : " << op.signal().getType();
 }
diff --git a/lib/Dialect/RTL/RTLOps.cpp b/lib/Dialect/RTL/RTLOps.cpp
index b0faa171c0..e9bfda67a7 100644
--- a/lib/Dialect/RTL/RTLOps.cpp
+++ b/lib/Dialect/RTL/RTLOps.cpp
@@ -37,7 +37,7 @@ bool rtl::isCombinatorial(Operation *op) {
 static void printConstantOp(OpAsmPrinter &p, ConstantOp &op) {
   p << "rtl.constant ";
   p.printAttribute(op.valueAttr());
-  p.printOptionalAttrDict(op.getAttrs(), /*elidedAttrs=*/{"value"});
+  p.printOptionalAttrDict(op->getAttrs(), /*elidedAttrs=*/{"value"});
 }
 
 static ParseResult parseConstantOp(OpAsmParser &parser,
@@ -812,7 +812,7 @@ static void print(OpAsmPrinter &printer, rtl::StructCreateOp op) {
   printer << op.getOperationName() << " (";
   printer.printOperands(op.input());
   printer << ")";
-  printer.printOptionalAttrDict(op.getAttrs());
+  printer.printOptionalAttrDict(op->getAttrs());
   printer << " : " << op.getType();
 }
 
@@ -842,7 +842,7 @@ static ParseResult parseStructExplodeOp(OpAsmParser &parser,
 static void print(OpAsmPrinter &printer, rtl::StructExplodeOp op) {
   printer << op.getOperationName() << " ";
   printer.printOperand(op.input());
-  printer.printOptionalAttrDict(op.getAttrs());
+  printer.printOptionalAttrDict(op->getAttrs());
   printer << " : " << op.input().getType();
 }
 
@@ -879,7 +879,7 @@ static void print(OpAsmPrinter &printer, rtl::StructExtractOp op) {
   printer << op.getOperationName() << " ";
   printer.printOperand(op.input());
   printer << "[\"" << op.field() << "\"]";
-  printer.printOptionalAttrDict(op.getAttrs(), {"field"});
+  printer.printOptionalAttrDict(op->getAttrs(), {"field"});
   printer << " : " << op.input().getType();
 }
 
@@ -926,7 +926,7 @@ static void print(OpAsmPrinter &printer, rtl::StructInjectOp op) {
   printer.printOperand(op.input());
   printer << "[\"" << op.field() << "\"], ";
   printer.printOperand(op.newValue());
-  printer.printOptionalAttrDict(op.getAttrs(), {"field"});
+  printer.printOptionalAttrDict(op->getAttrs(), {"field"});
   printer << " : " << op.input().getType();
 }
 
diff --git a/lib/Dialect/RTL/RTLTypes.cpp b/lib/Dialect/RTL/RTLTypes.cpp
index ac1e4019b6..7760cca507 100644
--- a/lib/Dialect/RTL/RTLTypes.cpp
+++ b/lib/Dialect/RTL/RTLTypes.cpp
@@ -15,7 +15,9 @@
 #include "circt/Support/LLVM.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/BuiltinTypes.h"
+#include "mlir/IR/Diagnostics.h"
 #include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/StorageUniquerSupport.h"
 #include "mlir/IR/Types.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/TypeSwitch.h"
@@ -122,8 +124,9 @@ static ParseResult parseRTLElementType(Type &result, DialectAsmParser &p) {
     llvm::StringRef mnemonic;
     if (p.parseKeyword(&mnemonic))
       llvm_unreachable("should have an array or inout keyword here");
-    result = generatedTypeParser(p.getBuilder().getContext(), p, mnemonic);
-    return result ? success() : failure();
+    auto parseResult =
+        generatedTypeParser(p.getBuilder().getContext(), p, mnemonic, result);
+    return parseResult.hasValue() ? success() : failure();
   }
 
   return p.parseType(result);
@@ -204,7 +207,8 @@ Type ArrayType::parse(MLIRContext *ctxt, DialectAsmParser &p) {
   }
 
   auto loc = p.getEncodedSourceLoc(p.getCurrentLocation());
-  if (failed(verifyConstructionInvariants(loc, inner, dims[0])))
+  if (failed(verify(mlir::detail::getDefaultDiagnosticEmitFn(loc), inner,
+                    dims[0])))
     return Type();
 
   return get(ctxt, inner, dims[0]);
@@ -216,11 +220,10 @@ void ArrayType::print(DialectAsmPrinter &p) const {
   p << '>';
 }
 
-LogicalResult ArrayType::verifyConstructionInvariants(Location loc,
-                                                      Type innerType,
-                                                      size_t size) {
+LogicalResult ArrayType::verify(function_ref<InFlightDiagnostic()> emitError,
+                                Type innerType, size_t size) {
   if (hasRTLInOutType(innerType))
-    return emitError(loc, "rtl.array cannot contain InOut types");
+    return emitError() << "rtl.array cannot contain InOut types";
   return success();
 }
 
@@ -241,7 +244,8 @@ Type UnpackedArrayType::parse(MLIRContext *ctxt, DialectAsmParser &p) {
   }
 
   auto loc = p.getEncodedSourceLoc(p.getCurrentLocation());
-  if (failed(verifyConstructionInvariants(loc, inner, dims[0])))
+  if (failed(verify(mlir::detail::getDefaultDiagnosticEmitFn(loc), inner,
+                    dims[0])))
     return Type();
 
   return get(ctxt, inner, dims[0]);
@@ -253,11 +257,11 @@ void UnpackedArrayType::print(DialectAsmPrinter &p) const {
   p << '>';
 }
 
-LogicalResult UnpackedArrayType::verifyConstructionInvariants(Location loc,
-                                                              Type innerType,
-                                                              size_t size) {
+LogicalResult
+UnpackedArrayType::verify(function_ref<InFlightDiagnostic()> emitError,
+                          Type innerType, size_t size) {
   if (!isRTLValueType(innerType))
-    return emitError(loc, "invalid element for sv.uarray type");
+    return emitError() << "invalid element for sv.uarray type";
   return success();
 }
 
@@ -271,7 +275,7 @@ Type InOutType::parse(MLIRContext *ctxt, DialectAsmParser &p) {
     return Type();
 
   auto loc = p.getEncodedSourceLoc(p.getCurrentLocation());
-  if (failed(verifyConstructionInvariants(loc, inner)))
+  if (failed(verify(mlir::detail::getDefaultDiagnosticEmitFn(loc), inner)))
     return Type();
 
   return get(ctxt, inner);
@@ -283,10 +287,10 @@ void InOutType::print(DialectAsmPrinter &p) const {
   p << '>';
 }
 
-LogicalResult InOutType::verifyConstructionInvariants(Location loc,
-                                                      Type innerType) {
+LogicalResult InOutType::verify(function_ref<InFlightDiagnostic()> emitError,
+                                Type innerType) {
   if (!isRTLValueType(innerType))
-    return emitError(loc, "invalid element for rtl.inout type");
+    return emitError() << "invalid element for rtl.inout type";
   return success();
 }
 
@@ -296,7 +300,11 @@ Type RTLDialect::parseType(DialectAsmParser &parser) const {
   llvm::StringRef mnemonic;
   if (parser.parseKeyword(&mnemonic))
     return Type();
-  return generatedTypeParser(getContext(), parser, mnemonic);
+  Type type;
+  auto parseResult = generatedTypeParser(getContext(), parser, mnemonic, type);
+  if (parseResult.hasValue())
+    return type;
+  return Type();
 }
 
 /// Print a type registered to this dialect. Try the tblgen'd type printer
diff --git a/lib/Dialect/SV/SVOps.cpp b/lib/Dialect/SV/SVOps.cpp
index b8dc4bc41e..58831f3bac 100644
--- a/lib/Dialect/SV/SVOps.cpp
+++ b/lib/Dialect/SV/SVOps.cpp
@@ -591,7 +591,7 @@ static ParseResult parseCaseZOp(OpAsmParser &parser, OperationState &result) {
 
 static void printCaseZOp(OpAsmPrinter &p, CaseZOp op) {
   p << "sv.casez" << ' ' << op.cond() << " : " << op.cond().getType();
-  p.printOptionalAttrDict(op.getAttrs(), /*elidedAttrs=*/{"casePatterns"});
+  p.printOptionalAttrDict(op->getAttrs(), /*elidedAttrs=*/{"casePatterns"});
 
   for (auto caseInfo : op.getCases()) {
     p.printNewline();
diff --git a/lib/Dialect/SV/SVTypes.cpp b/lib/Dialect/SV/SVTypes.cpp
index 28f5f04278..c9e107517d 100644
--- a/lib/Dialect/SV/SVTypes.cpp
+++ b/lib/Dialect/SV/SVTypes.cpp
@@ -84,7 +84,9 @@ Type SVDialect::parseType(DialectAsmParser &parser) const {
   auto loc = parser.getCurrentLocation();
   if (parser.parseKeyword(&mnemonic))
     return Type();
-  if (auto type = generatedTypeParser(getContext(), parser, mnemonic))
+  Type type;
+  auto parseResult = generatedTypeParser(getContext(), parser, mnemonic, type);
+  if (parseResult.hasValue())
     return type;
   parser.emitError(loc, "Failed to parse type sv.") << mnemonic << "\n";
   return Type();
diff --git a/llvm b/llvm
index c68d2895a1..c68b560be3 160000
--- a/llvm
+++ b/llvm
@@ -1 +1 @@
-Subproject commit c68d2895a1f4019b387c69d1e5eec31b0eb5e7b0
+Subproject commit c68b560be381e831fd72c6b8b8909427e4e2ff36
diff --git a/test/Dialect/LLHD/Export/verilog_sig.mlir b/test/Dialect/LLHD/Export/verilog_sig.mlir
index 58dcf779cd..674f65982b 100644
--- a/test/Dialect/LLHD/Export/verilog_sig.mlir
+++ b/test/Dialect/LLHD/Export/verilog_sig.mlir
@@ -20,14 +20,3 @@ llhd.entity @check_sig () -> () {
   // CHECK-NEXT: assign _[[C]] = #(0ns) _[[A]] ? _[[A]] : _[[C]];
   llhd.drv %3, %0 after %6 if %0 : !llhd.sig<i1>
 }
-
-// -----
-
-llhd.entity @check_invalid_drv_time () -> () {
-  %0 = llhd.const 1 : i1
-  %1 = llhd.sig "sigI1" %0 : i1
-  // expected-error @+2 {{Not possible to translate a time attribute with 0 real time and non-1 delta.}}
-  // expected-error @+1 {{Operation not supported!}}
-  %2 = llhd.const #llhd.time<0ns, 0d, 0e> : !llhd.time
-  llhd.drv %1, %0 after %2 : !llhd.sig<i1>
-}
diff --git a/test/Dialect/LLHD/Export/verilog_sig_errors.mlir b/test/Dialect/LLHD/Export/verilog_sig_errors.mlir
new file mode 100644
index 0000000000..af9f733651
--- /dev/null
+++ b/test/Dialect/LLHD/Export/verilog_sig_errors.mlir
@@ -0,0 +1,10 @@
+//RUN: circt-translate --export-llhd-verilog -split-input-file -verify-diagnostics %s
+
+llhd.entity @check_invalid_drv_time () -> () {
+  %0 = llhd.const 1 : i1
+  %1 = llhd.sig "sigI1" %0 : i1
+  // expected-error @+2 {{Not possible to translate a time attribute with 0 real time and non-1 delta.}}
+  // expected-error @+1 {{Operation not supported!}}
+  %2 = llhd.const #llhd.time<0ns, 0d, 0e> : !llhd.time
+  llhd.drv %1, %0 after %2 : !llhd.sig<i1>
+}
diff --git a/test/Dialect/LLHD/IR/connect-errors.mlir b/test/Dialect/LLHD/IR/connect-errors.mlir
new file mode 100644
index 0000000000..08496f2613
--- /dev/null
+++ b/test/Dialect/LLHD/IR/connect-errors.mlir
@@ -0,0 +1,17 @@
+// RUN: circt-opt %s -split-input-file -verify-diagnostics
+
+// expected-note @+1 {{prior use here}}
+llhd.entity @connect_different_types(%in: !llhd.sig<i8>) -> (%out: !llhd.sig<i32>) {
+  // expected-error @+1 {{use of value '%out' expects different type}}
+  llhd.con %in, %out : !llhd.sig<i8>
+  // expected-error @+1 {{expected operation}}
+}
+
+// -----
+
+llhd.entity @connect_non_signals(%in: !llhd.sig<i32>) -> (%out: !llhd.sig<i32>) {
+  %0 = llhd.prb %in : !llhd.sig<i32>
+  %1 = llhd.prb %out : !llhd.sig<i32>
+  // expected-error @+1 {{'llhd.con' op operand #0 must be LLHD sig type}}
+  llhd.con %0, %1 : i32
+}
diff --git a/test/Dialect/LLHD/IR/connect.mlir b/test/Dialect/LLHD/IR/connect.mlir
index 6377281b04..f993dec29f 100644
--- a/test/Dialect/LLHD/IR/connect.mlir
+++ b/test/Dialect/LLHD/IR/connect.mlir
@@ -1,4 +1,4 @@
-// RUN: circt-opt %s -split-input-file -verify-diagnostics | FileCheck %s
+// RUN: circt-opt %s -split-input-file | FileCheck %s
 
 // CHECK-LABEL: @connect_ports
 // CHECK-SAME: (%[[IN:.+]] : [[TYPE:.+]]) ->
@@ -7,20 +7,3 @@
 llhd.entity @connect_ports(%in: !llhd.sig<i32>) -> (%out: !llhd.sig<i32>) {
   llhd.con %in, %out : !llhd.sig<i32>
 }
-
-// -----
-
-// expected-note @+1 {{prior use here}}
-llhd.entity @connect_different_types(%in: !llhd.sig<i8>) -> (%out: !llhd.sig<i32>) {
-  // expected-error @+1 {{use of value '%out' expects different type}}
-  llhd.con %in, %out : !llhd.sig<i8>
-  // expected-error @+1 {{expected operation}}
-}
-// -----
-
-llhd.entity @connect_non_signals(%in: !llhd.sig<i32>) -> (%out: !llhd.sig<i32>) {
-  %0 = llhd.prb %in : !llhd.sig<i32>
-  %1 = llhd.prb %out : !llhd.sig<i32>
-  // expected-error @+1 {{'llhd.con' op operand #0 must be LLHD sig type}}
-  llhd.con %0, %1 : i32
-}
diff --git a/test/Dialect/LLHD/IR/extract-errors.mlir b/test/Dialect/LLHD/IR/extract-errors.mlir
new file mode 100644
index 0000000000..fe9abd72ed
--- /dev/null
+++ b/test/Dialect/LLHD/IR/extract-errors.mlir
@@ -0,0 +1,206 @@
+// RUN: circt-opt %s -mlir-print-op-generic -split-input-file -verify-diagnostics
+
+func @illegal_array_to_signal(%array : !llhd.array<3xi32>) {
+  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
+  %0 = llhd.extract_slice %array, 0 : !llhd.array<3xi32> -> !llhd.sig<!llhd.array<3xi32>>
+
+  return
+}
+
+// -----
+
+func @illegal_signal_to_array(%sig : !llhd.sig<!llhd.array<3xi32>>) {
+  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
+  %0 = llhd.extract_slice %sig, 0 : !llhd.sig<!llhd.array<3xi32>> -> !llhd.array<3xi32>
+
+  return
+}
+
+// -----
+
+func @illegal_array_element_type_mismatch(%sig : !llhd.sig<!llhd.array<3xi32>>) {
+  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
+  %0 = llhd.extract_slice %sig, 0 : !llhd.sig<!llhd.array<3xi32>> -> !llhd.sig<!llhd.array<2xi1>>
+
+  return
+}
+
+// -----
+
+func @illegal_result_array_too_big(%sig : !llhd.sig<!llhd.array<3xi32>>) {
+  // expected-error @+1 {{'start' + size of the slice have to be smaller or equal to the 'target' size}}
+  %0 = llhd.extract_slice %sig, 0 : !llhd.sig<!llhd.array<3xi32>> -> !llhd.sig<!llhd.array<4xi32>>
+
+  return
+}
+
+// -----
+
+func @illegal_int_to_sig(%c : i32) {
+  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
+  %0 = llhd.extract_slice %c, 0 : i32 -> !llhd.sig<i10>
+
+  return
+}
+
+// -----
+
+func @illegal_sig_to_int(%s : !llhd.sig<i32>) {
+  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
+  %0 = llhd.extract_slice %s, 0 : !llhd.sig<i32> -> i10
+
+  return
+}
+
+// -----
+
+func @illegal_out_too_big(%c : i32) {
+  // expected-error @+1 {{failed to verify that 'start' + size of the slice have to be smaller or equal to the 'target' size}}
+  %0 = llhd.extract_slice %c, 0 : i32 -> i40
+
+  return
+}
+
+// -----
+
+func @illegal_array_to_signal(%array : !llhd.array<3xi32>, %index : i32) {
+  // expected-error @+1 {{'target' and 'result' types have to match apart from their width}}
+  %0 = llhd.dyn_extract_slice %array, %index : (!llhd.array<3xi32>, i32) -> !llhd.sig<!llhd.array<3xi32>>
+
+  return
+}
+
+// -----
+
+func @illegal_signal_to_array(%sig : !llhd.sig<!llhd.array<3xi32>>, %index: i32) {
+  // expected-error @+1 {{'target' and 'result' types have to match apart from their width}}
+  %0 = llhd.dyn_extract_slice %sig, %index : (!llhd.sig<!llhd.array<3xi32>>, i32) -> !llhd.array<3xi32>
+
+  return
+}
+
+// -----
+
+func @illegal_array_element_type_mismatch(%sig : !llhd.sig<!llhd.array<3xi32>>, %index : i32) {
+  // expected-error @+1 {{'target' and 'result' types have to match apart from their width}}
+  %0 = llhd.dyn_extract_slice %sig, %index : (!llhd.sig<!llhd.array<3xi32>>, i32) -> !llhd.sig<!llhd.array<2xi1>>
+
+  return
+}
+
+// -----
+
+func @illegal_result_array_too_big(%sig : !llhd.sig<!llhd.array<3xi32>>, %index : i32) {
+  // expected-error @+1 {{the result width cannot be larger than the target operand width}}
+  %0 = llhd.dyn_extract_slice %sig, %index : (!llhd.sig<!llhd.array<3xi32>>, i32) -> !llhd.sig<!llhd.array<4xi32>>
+
+  return
+}
+
+// -----
+
+func @dyn_extract_slice_illegal_conversion(%s : !llhd.sig<i32>, %i : i1) {
+  // expected-error @+1 {{'llhd.dyn_extract_slice' op failed to verify that 'target' and 'result' types have to match apart from their width}}
+  %0 = llhd.dyn_extract_slice %s, %i : (!llhd.sig<i32>, i1) -> i10
+
+  return
+}
+
+// -----
+
+func @dyn_extract_slice_illegal_out_too_wide(%c : i32, %i : i1) {
+  // expected-error @+1 {{'llhd.dyn_extract_slice' op failed to verify that the result width cannot be larger than the target operand width}}
+  %0 = llhd.dyn_extract_slice %c, %i : (i32, i1) -> i40
+
+  return
+}
+
+// -----
+
+func @dyn_extract_slice_illegal_vec_element_conversion(%c : !llhd.array<1xi1>, %i : i1) {
+  // expected-error @+1 {{'llhd.dyn_extract_slice' op failed to verify that 'target' and 'result' types have to match apart from their width}}
+  %0 = llhd.dyn_extract_slice %c, %i : (!llhd.array<1xi1>, i1) -> !llhd.array<1xi10>
+
+  return
+}
+
+// -----
+
+func @extract_element_array_index_out_of_bounds(%array : !llhd.array<3xi1>) {
+  // expected-error @+1 {{'index' has to be smaller than the width of the 'target' type}}
+  %0 = llhd.extract_element %array, 3 : !llhd.array<3xi1> -> i1
+
+  return
+}
+
+// -----
+
+func @extract_element_tuple_index_out_of_bounds(%tup : tuple<i1, i2, i3>) {
+  // expected-error @+1 {{'index' has to be smaller than the width of the 'target' type}}
+  %0 = llhd.extract_element %tup, 3 : tuple<i1, i2, i3> -> i3
+
+  return
+}
+
+// -----
+
+func @extract_element_array_type_mismatch(%array : !llhd.array<3xi1>) {
+  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
+  %0 = llhd.extract_element %array, 0 : !llhd.array<3xi1> -> i2
+
+  return
+}
+
+// -----
+
+func @extract_element_tuple_type_mismatch(%tup : tuple<i1, i2, i3>) {
+  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
+  %0 = llhd.extract_element %tup, 0 : tuple<i1, i2, i3> -> i2
+
+  return
+}
+
+// -----
+
+func @extract_element_signal_type_mismatch(%sig : !llhd.sig<tuple<i1, i2, i3>>) {
+  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
+  %0 = llhd.extract_element %sig, 0 : !llhd.sig<tuple<i1, i2, i3>> -> !llhd.sig<i2>
+
+  return
+}
+
+// -----
+
+func @extract_element_illegal_signal_alias(%sig : !llhd.sig<tuple<i1, i2, i3>>) {
+  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
+  %0 = llhd.extract_element %sig, 0 : !llhd.sig<tuple<i1, i2, i3>> -> i1
+
+  return
+}
+
+// -----
+
+func @dyn_extract_element_array_type_mismatch(%index : i2, %array : !llhd.array<3xi1>) {
+  // expected-error @+1 {{'result' must be the element type of the 'target' array, in case 'target' is a signal of an array, 'result' also is a signal of the array element type}}
+  %0 = llhd.dyn_extract_element %array, %index : (!llhd.array<3xi1>, i2) -> i2
+
+  return
+}
+
+// -----
+
+func @dyn_extract_element_signal_type_mismatch(%index : i2, %sig : !llhd.sig<!llhd.array<3xi1>>) {
+  // expected-error @+1 {{'result' must be the element type of the 'target' array, in case 'target' is a signal of an array, 'result' also is a signal of the array element type}}
+  %0 = llhd.dyn_extract_element %sig, %index : (!llhd.sig<!llhd.array<3xi1>>, i2) -> !llhd.sig<i2>
+
+  return
+}
+
+// -----
+
+func @dyn_extract_element_illegal_signal_alias(%index : i2, %sig : !llhd.sig<!llhd.array<3xi1>>) {
+  // expected-error @+1 {{'result' must be the element type of the 'target' array, in case 'target' is a signal of an array, 'result' also is a signal of the array element type}}
+  %0 = llhd.dyn_extract_element %sig, %index : (!llhd.sig<!llhd.array<3xi1>>, i2) -> i1
+
+  return
+}
diff --git a/test/Dialect/LLHD/IR/extract.mlir b/test/Dialect/LLHD/IR/extract.mlir
index 73e61b1ccf..1e5246f464 100644
--- a/test/Dialect/LLHD/IR/extract.mlir
+++ b/test/Dialect/LLHD/IR/extract.mlir
@@ -163,210 +163,3 @@ func @dyn_extract_element_signals_of_arrays(%index : i32, %array1 : !llhd.sig<!l
 
   return
 }
-
-// -----
-
-func @illegal_array_to_signal(%array : !llhd.array<3xi32>) {
-  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
-  %0 = llhd.extract_slice %array, 0 : !llhd.array<3xi32> -> !llhd.sig<!llhd.array<3xi32>>
-
-  return
-}
-
-// -----
-
-func @illegal_signal_to_array(%sig : !llhd.sig<!llhd.array<3xi32>>) {
-  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
-  %0 = llhd.extract_slice %sig, 0 : !llhd.sig<!llhd.array<3xi32>> -> !llhd.array<3xi32>
-
-  return
-}
-
-// -----
-
-func @illegal_array_element_type_mismatch(%sig : !llhd.sig<!llhd.array<3xi32>>) {
-  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
-  %0 = llhd.extract_slice %sig, 0 : !llhd.sig<!llhd.array<3xi32>> -> !llhd.sig<!llhd.array<2xi1>>
-
-  return
-}
-
-// -----
-
-func @illegal_result_array_too_big(%sig : !llhd.sig<!llhd.array<3xi32>>) {
-  // expected-error @+1 {{'start' + size of the slice have to be smaller or equal to the 'target' size}}
-  %0 = llhd.extract_slice %sig, 0 : !llhd.sig<!llhd.array<3xi32>> -> !llhd.sig<!llhd.array<4xi32>>
-
-  return
-}
-
-// -----
-
-func @illegal_int_to_sig(%c : i32) {
-  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
-  %0 = llhd.extract_slice %c, 0 : i32 -> !llhd.sig<i10>
-
-  return
-}
-
-// -----
-
-func @illegal_sig_to_int(%s : !llhd.sig<i32>) {
-  // expected-error @+1 {{failed to verify that 'target' and 'result' have to be both either signless integers, signals or arrays with the same element type}}
-  %0 = llhd.extract_slice %s, 0 : !llhd.sig<i32> -> i10
-
-  return
-}
-
-// -----
-
-func @illegal_out_too_big(%c : i32) {
-  // expected-error @+1 {{failed to verify that 'start' + size of the slice have to be smaller or equal to the 'target' size}}
-  %0 = llhd.extract_slice %c, 0 : i32 -> i40
-
-  return
-}
-
-// -----
-
-func @illegal_array_to_signal(%array : !llhd.array<3xi32>, %index : i32) {
-  // expected-error @+1 {{'target' and 'result' types have to match apart from their width}}
-  %0 = llhd.dyn_extract_slice %array, %index : (!llhd.array<3xi32>, i32) -> !llhd.sig<!llhd.array<3xi32>>
-
-  return
-}
-
-// -----
-
-func @illegal_signal_to_array(%sig : !llhd.sig<!llhd.array<3xi32>>, %index: i32) {
-  // expected-error @+1 {{'target' and 'result' types have to match apart from their width}}
-  %0 = llhd.dyn_extract_slice %sig, %index : (!llhd.sig<!llhd.array<3xi32>>, i32) -> !llhd.array<3xi32>
-
-  return
-}
-
-// -----
-
-func @illegal_array_element_type_mismatch(%sig : !llhd.sig<!llhd.array<3xi32>>, %index : i32) {
-  // expected-error @+1 {{'target' and 'result' types have to match apart from their width}}
-  %0 = llhd.dyn_extract_slice %sig, %index : (!llhd.sig<!llhd.array<3xi32>>, i32) -> !llhd.sig<!llhd.array<2xi1>>
-
-  return
-}
-
-// -----
-
-func @illegal_result_array_too_big(%sig : !llhd.sig<!llhd.array<3xi32>>, %index : i32) {
-  // expected-error @+1 {{the result width cannot be larger than the target operand width}}
-  %0 = llhd.dyn_extract_slice %sig, %index : (!llhd.sig<!llhd.array<3xi32>>, i32) -> !llhd.sig<!llhd.array<4xi32>>
-
-  return
-}
-
-// -----
-
-func @dyn_extract_slice_illegal_conversion(%s : !llhd.sig<i32>, %i : i1) {
-  // expected-error @+1 {{'llhd.dyn_extract_slice' op failed to verify that 'target' and 'result' types have to match apart from their width}}
-  %0 = llhd.dyn_extract_slice %s, %i : (!llhd.sig<i32>, i1) -> i10
-
-  return
-}
-
-// -----
-
-func @dyn_extract_slice_illegal_out_too_wide(%c : i32, %i : i1) {
-  // expected-error @+1 {{'llhd.dyn_extract_slice' op failed to verify that the result width cannot be larger than the target operand width}}
-  %0 = llhd.dyn_extract_slice %c, %i : (i32, i1) -> i40
-
-  return
-}
-
-// -----
-
-func @dyn_extract_slice_illegal_vec_element_conversion(%c : !llhd.array<1xi1>, %i : i1) {
-  // expected-error @+1 {{'llhd.dyn_extract_slice' op failed to verify that 'target' and 'result' types have to match apart from their width}}
-  %0 = llhd.dyn_extract_slice %c, %i : (!llhd.array<1xi1>, i1) -> !llhd.array<1xi10>
-
-  return
-}
-
-// -----
-
-func @extract_element_array_index_out_of_bounds(%array : !llhd.array<3xi1>) {
-  // expected-error @+1 {{'index' has to be smaller than the width of the 'target' type}}
-  %0 = llhd.extract_element %array, 3 : !llhd.array<3xi1> -> i1
-
-  return
-}
-
-// -----
-
-func @extract_element_tuple_index_out_of_bounds(%tup : tuple<i1, i2, i3>) {
-  // expected-error @+1 {{'index' has to be smaller than the width of the 'target' type}}
-  %0 = llhd.extract_element %tup, 3 : tuple<i1, i2, i3> -> i3
-
-  return
-}
-
-// -----
-
-func @extract_element_array_type_mismatch(%array : !llhd.array<3xi1>) {
-  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
-  %0 = llhd.extract_element %array, 0 : !llhd.array<3xi1> -> i2
-
-  return
-}
-
-// -----
-
-func @extract_element_tuple_type_mismatch(%tup : tuple<i1, i2, i3>) {
-  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
-  %0 = llhd.extract_element %tup, 0 : tuple<i1, i2, i3> -> i2
-
-  return
-}
-
-// -----
-
-func @extract_element_signal_type_mismatch(%sig : !llhd.sig<tuple<i1, i2, i3>>) {
-  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
-  %0 = llhd.extract_element %sig, 0 : !llhd.sig<tuple<i1, i2, i3>> -> !llhd.sig<i2>
-
-  return
-}
-
-// -----
-
-func @extract_element_illegal_signal_alias(%sig : !llhd.sig<tuple<i1, i2, i3>>) {
-  // expected-error @+1 {{'result' type must match the type of 'target' at position 'index', or in case 'target' is a signal, it must be a signal of the underlying type of 'target' at position 'index'}}
-  %0 = llhd.extract_element %sig, 0 : !llhd.sig<tuple<i1, i2, i3>> -> i1
-
-  return
-}
-
-// -----
-
-func @dyn_extract_element_array_type_mismatch(%index : i2, %array : !llhd.array<3xi1>) {
-  // expected-error @+1 {{'result' must be the element type of the 'target' array, in case 'target' is a signal of an array, 'result' also is a signal of the array element type}}
-  %0 = llhd.dyn_extract_element %array, %index : (!llhd.array<3xi1>, i2) -> i2
-
-  return
-}
-
-// -----
-
-func @dyn_extract_element_signal_type_mismatch(%index : i2, %sig : !llhd.sig<!llhd.array<3xi1>>) {
-  // expected-error @+1 {{'result' must be the element type of the 'target' array, in case 'target' is a signal of an array, 'result' also is a signal of the array element type}}
-  %0 = llhd.dyn_extract_element %sig, %index : (!llhd.sig<!llhd.array<3xi1>>, i2) -> !llhd.sig<i2>
-
-  return
-}
-
-// -----
-
-func @dyn_extract_element_illegal_signal_alias(%index : i2, %sig : !llhd.sig<!llhd.array<3xi1>>) {
-  // expected-error @+1 {{'result' must be the element type of the 'target' array, in case 'target' is a signal of an array, 'result' also is a signal of the array element type}}
-  %0 = llhd.dyn_extract_element %sig, %index : (!llhd.sig<!llhd.array<3xi1>>, i2) -> i1
-
-  return
-}
diff --git a/test/Dialect/LLHD/IR/insert-errors.mlir b/test/Dialect/LLHD/IR/insert-errors.mlir
new file mode 100644
index 0000000000..8371d6d940
--- /dev/null
+++ b/test/Dialect/LLHD/IR/insert-errors.mlir
@@ -0,0 +1,62 @@
+// RUN: circt-opt %s -mlir-print-op-generic -split-input-file -verify-diagnostics
+
+func @illegal_kind(%c : i32, %array : !llhd.array<2xi32>) {
+  // expected-error @+1 {{failed to verify that 'target' and 'slice' have to be both either signless integers or arrays with the same element type}}
+  %0 = llhd.insert_slice %array, %c, 0 : !llhd.array<2xi32>, i32
+
+  return
+}
+
+// -----
+
+func @illegal_elemental_type(%slice : !llhd.array<1xi1>, %array : !llhd.array<2xi32>) {
+  // expected-error @+1 {{failed to verify that 'target' and 'slice' have to be both either signless integers or arrays with the same element type}}
+  %0 = llhd.insert_slice %array, %slice, 0 : !llhd.array<2xi32>, !llhd.array<1xi1>
+
+  return
+}
+
+// -----
+
+func @insert_slice_illegal_start_index_int(%slice : i16, %c : i32) {
+  // expected-error @+1 {{failed to verify that 'start' + size of the 'slice' have to be smaller or equal to the 'target' size}}
+  %0 = llhd.insert_slice %c, %slice, 20 : i32, i16
+
+  return
+}
+
+// -----
+
+func @insert_slice_illegal_start_index_array(%slice : !llhd.array<2xi1>, %array : !llhd.array<3xi1>) {
+  // expected-error @+1 {{failed to verify that 'start' + size of the 'slice' have to be smaller or equal to the 'target' size}}
+  %0 = llhd.insert_slice %array, %slice, 2 : !llhd.array<3xi1>, !llhd.array<2xi1>
+
+  return
+}
+
+// -----
+
+func @insert_element_index_out_of_bounds(%e : i1, %array : !llhd.array<3xi1>) {
+  // expected-error @+1 {{failed to verify that 'index' has to be smaller than the 'target' size}}
+  %0 = llhd.insert_element %array, %e, 3 : !llhd.array<3xi1>, i1
+
+  return
+}
+
+// -----
+
+func @insert_element_type_mismatch_array(%e : i2, %array : !llhd.array<3xi1>) {
+  // expected-error @+1 {{failed to verify that 'element' type has to match type at 'index' of 'target'}}
+  %0 = llhd.insert_element %array, %e, 0 : !llhd.array<3xi1>, i2
+
+  return
+}
+
+// -----
+
+func @insert_element_type_mismatch_tuple(%e : i2, %tup : tuple<i2, i1, i2>) {
+  // expected-error @+1 {{failed to verify that 'element' type has to match type at 'index' of 'target'}}
+  %0 = llhd.insert_element %tup, %e, 1 : tuple<i2, i1, i2>, i2
+
+  return
+}
diff --git a/test/Dialect/LLHD/IR/insert.mlir b/test/Dialect/LLHD/IR/insert.mlir
index b7127804a1..2b12eedfec 100644
--- a/test/Dialect/LLHD/IR/insert.mlir
+++ b/test/Dialect/LLHD/IR/insert.mlir
@@ -50,66 +50,3 @@ func @insert_element_arrays(%v1 : !llhd.array<4xi1>, %v8 : !llhd.array<4xi8>, %i
 
   return
 }
-
-// -----
-
-func @illegal_kind(%c : i32, %array : !llhd.array<2xi32>) {
-  // expected-error @+1 {{failed to verify that 'target' and 'slice' have to be both either signless integers or arrays with the same element type}}
-  %0 = llhd.insert_slice %array, %c, 0 : !llhd.array<2xi32>, i32
-
-  return
-}
-
-// -----
-
-func @illegal_elemental_type(%slice : !llhd.array<1xi1>, %array : !llhd.array<2xi32>) {
-  // expected-error @+1 {{failed to verify that 'target' and 'slice' have to be both either signless integers or arrays with the same element type}}
-  %0 = llhd.insert_slice %array, %slice, 0 : !llhd.array<2xi32>, !llhd.array<1xi1>
-
-  return
-}
-
-// -----
-
-func @insert_slice_illegal_start_index_int(%slice : i16, %c : i32) {
-  // expected-error @+1 {{failed to verify that 'start' + size of the 'slice' have to be smaller or equal to the 'target' size}}
-  %0 = llhd.insert_slice %c, %slice, 20 : i32, i16
-
-  return
-}
-
-// -----
-
-func @insert_slice_illegal_start_index_array(%slice : !llhd.array<2xi1>, %array : !llhd.array<3xi1>) {
-  // expected-error @+1 {{failed to verify that 'start' + size of the 'slice' have to be smaller or equal to the 'target' size}}
-  %0 = llhd.insert_slice %array, %slice, 2 : !llhd.array<3xi1>, !llhd.array<2xi1>
-
-  return
-}
-
-// -----
-
-func @insert_element_index_out_of_bounds(%e : i1, %array : !llhd.array<3xi1>) {
-  // expected-error @+1 {{failed to verify that 'index' has to be smaller than the 'target' size}}
-  %0 = llhd.insert_element %array, %e, 3 : !llhd.array<3xi1>, i1
-
-  return
-}
-
-// -----
-
-func @insert_element_type_mismatch_array(%e : i2, %array : !llhd.array<3xi1>) {
-  // expected-error @+1 {{failed to verify that 'element' type has to match type at 'index' of 'target'}}
-  %0 = llhd.insert_element %array, %e, 0 : !llhd.array<3xi1>, i2
-
-  return
-}
-
-// -----
-
-func @insert_element_type_mismatch_tuple(%e : i2, %tup : tuple<i2, i1, i2>) {
-  // expected-error @+1 {{failed to verify that 'element' type has to match type at 'index' of 'target'}}
-  %0 = llhd.insert_element %tup, %e, 1 : tuple<i2, i1, i2>, i2
-
-  return
-}
diff --git a/test/Dialect/LLHD/IR/inst-errors.mlir b/test/Dialect/LLHD/IR/inst-errors.mlir
new file mode 100644
index 0000000000..0ffe1de2a2
--- /dev/null
+++ b/test/Dialect/LLHD/IR/inst-errors.mlir
@@ -0,0 +1,43 @@
+//RUN: circt-opt %s -split-input-file -verify-diagnostics
+
+// Testing Objectives:
+// * inst can only be used in entities
+// * inst must always refer to a valid proc or entity (match symbol name, input and output operands)
+// * syntax: no inputs and outputs, one input zero outputs, zero inputs one output, multiple inputs and outputs
+// * check that number of inputs and number of outputs are verified separately
+
+llhd.proc @empty_proc() -> () {
+  llhd.halt
+}
+
+llhd.proc @fail() -> () {
+  // expected-error @+1 {{expects parent op 'llhd.entity'}}
+  llhd.inst "empty" @empty_proc() -> () : () -> ()
+  llhd.halt
+}
+
+// -----
+
+llhd.entity @operand_count_mismatch(%arg : !llhd.sig<i32>) -> () {}
+
+llhd.entity @caller(%arg : !llhd.sig<i32>) -> () {
+  // expected-error @+1 {{incorrect number of inputs for entity instantiation}}
+  llhd.inst "mismatch" @operand_count_mismatch() -> (%arg) : () -> (!llhd.sig<i32>)
+}
+
+// -----
+
+llhd.entity @caller() -> () {
+  // expected-error @+1 {{does not reference a valid proc or entity}}
+  llhd.inst "does_not_exist" @does_not_exist() -> () : () -> ()
+}
+
+// -----
+
+llhd.entity @empty() -> () {}
+
+llhd.entity @test_uniqueness() -> () {
+  llhd.inst "inst" @empty() -> () : () -> ()
+  // expected-error @+1 {{Redefinition of instance named 'inst'!}}
+  llhd.inst "inst" @empty() -> () : () -> ()
+}
diff --git a/test/Dialect/LLHD/IR/inst.mlir b/test/Dialect/LLHD/IR/inst.mlir
index 6e088f4770..2367c01eab 100644
--- a/test/Dialect/LLHD/IR/inst.mlir
+++ b/test/Dialect/LLHD/IR/inst.mlir
@@ -59,41 +59,3 @@ llhd.entity @caller(%arg0 : !llhd.sig<i32>, %arg1 : !llhd.sig<i16>) -> (%out0 :
   "llhd.inst"(%arg0, %arg1, %out0, %out1) {callee=@proc, operand_segment_sizes=dense<[2,2]> : vector<2xi32>, name="proc"} : (!llhd.sig<i32>, !llhd.sig<i16>, !llhd.sig<i8>, !llhd.sig<i4>) -> ()
   // CHECK-NEXT: }
 }
-
-// -----
-
-llhd.proc @empty_proc() -> () {
-  llhd.halt
-}
-
-llhd.proc @fail() -> () {
-  // expected-error @+1 {{expects parent op 'llhd.entity'}}
-  llhd.inst "empty" @empty_proc() -> () : () -> ()
-  llhd.halt
-}
-
-// -----
-
-llhd.entity @operand_count_mismatch(%arg : !llhd.sig<i32>) -> () {}
-
-llhd.entity @caller(%arg : !llhd.sig<i32>) -> () {
-  // expected-error @+1 {{incorrect number of inputs for entity instantiation}}
-  llhd.inst "mismatch" @operand_count_mismatch() -> (%arg) : () -> (!llhd.sig<i32>)
-}
-
-// -----
-
-llhd.entity @caller() -> () {
-  // expected-error @+1 {{does not reference a valid proc or entity}}
-  llhd.inst "does_not_exist" @does_not_exist() -> () : () -> ()
-}
-
-// -----
-
-llhd.entity @empty() -> () {}
-
-llhd.entity @test_uniqueness() -> () {
-  llhd.inst "inst" @empty() -> () : () -> ()
-  // expected-error @+1 {{Redefinition of instance named 'inst'!}}
-  llhd.inst "inst" @empty() -> () : () -> ()
-}
diff --git a/test/Dialect/LLHD/IR/memory-errors.mlir b/test/Dialect/LLHD/IR/memory-errors.mlir
new file mode 100644
index 0000000000..12ad241f48
--- /dev/null
+++ b/test/Dialect/LLHD/IR/memory-errors.mlir
@@ -0,0 +1,9 @@
+// RUN: circt-opt %s -mlir-print-op-generic -split-input-file -verify-diagnostics
+
+// expected-note @+1 {{prior use here}}
+func @check_illegal_store(%i1Ptr : !llhd.ptr<i1>, %i32Const : i32) {
+  // expected-error @+1 {{use of value '%i32Const' expects different type than prior uses: 'i1' vs 'i32'}}
+  llhd.store %i1Ptr, %i32Const : !llhd.ptr<i1>
+
+  return
+}
diff --git a/test/Dialect/LLHD/IR/memory.mlir b/test/Dialect/LLHD/IR/memory.mlir
index 7c92a331e4..50a32d57bf 100644
--- a/test/Dialect/LLHD/IR/memory.mlir
+++ b/test/Dialect/LLHD/IR/memory.mlir
@@ -47,13 +47,3 @@ func @check_store(%int : !llhd.ptr<i32>, %intC : i32 , %array : !llhd.ptr<!llhd.
 
   return
 }
-
-// -----
-
-// expected-note @+1 {{prior use here}}
-func @check_illegal_store(%i1Ptr : !llhd.ptr<i1>, %i32Const : i32) {
-  // expected-error @+1 {{use of value '%i32Const' expects different type than prior uses: 'i1' vs 'i32'}}
-  llhd.store %i1Ptr, %i32Const : !llhd.ptr<i1>
-
-  return
-}
diff --git a/test/Dialect/LLHD/IR/reg.mlir b/test/Dialect/LLHD/IR/reg.mlir
index b23effd8eb..2a8f891a4a 100644
--- a/test/Dialect/LLHD/IR/reg.mlir
+++ b/test/Dialect/LLHD/IR/reg.mlir
@@ -20,4 +20,4 @@ llhd.entity @check_reg (%in64 : !llhd.sig<i64>) -> () {
   "llhd.reg"(%in64, %c64, %in64, %c1, %c1, %time, %time, %c1) {modes=[0,1], gateMask=[0,1], operand_segment_sizes=dense<[1,2,2,2,1]> : vector<5xi32>} : (!llhd.sig<i64>, i64, !llhd.sig<i64>, i1, i1, !llhd.time, !llhd.time, i1) -> ()
 }
 
-// TODO: add verification tests (expected-error tests)
+// TODO: add verification tests in reg-errors.mlir (expected-error tests)
diff --git a/test/Dialect/LLHD/IR/signal-errors.mlir b/test/Dialect/LLHD/IR/signal-errors.mlir
new file mode 100644
index 0000000000..9626973244
--- /dev/null
+++ b/test/Dialect/LLHD/IR/signal-errors.mlir
@@ -0,0 +1,32 @@
+// RUN: circt-opt %s -mlir-print-op-generic -split-input-file -verify-diagnostics
+
+// expected-error @+3 {{failed to verify that type of 'init' and underlying type of 'signal' have to match.}}
+llhd.entity @check_illegal_sig () -> () {
+  %cI1 = llhd.const 0 : i1
+  %sig1 = "llhd.sig"(%cI1) {name="foo"} : (i1) -> !llhd.sig<i32>
+}
+
+// -----
+
+// expected-error @+2 {{failed to verify that type of 'result' and underlying type of 'signal' have to match.}}
+llhd.entity @check_illegal_prb (%sig : !llhd.sig<i1>) -> () {
+  %prb = "llhd.prb"(%sig) {} : (!llhd.sig<i1>) -> i32
+}
+
+// -----
+
+// expected-error @+4 {{failed to verify that type of 'value' and underlying type of 'signal' have to match.}}
+llhd.entity @check_illegal_drv (%sig : !llhd.sig<i1>) -> () {
+  %c = llhd.const 0 : i32
+  %time = llhd.const #llhd.time<1ns, 0d, 0e> : !llhd.time
+  "llhd.drv"(%sig, %c, %time) {} : (!llhd.sig<i1>, i32, !llhd.time) -> ()
+}
+
+// -----
+
+// expected-error @+4 {{Redefinition of signal named 'sigI1'!}}
+llhd.entity @check_unique_sig_names () -> () {
+  %cI1 = llhd.const 0 : i1
+  %sig1 = llhd.sig "sigI1" %cI1 : i1
+  %sig2 = llhd.sig "sigI1" %cI1 : i1
+}
diff --git a/test/Dialect/LLHD/IR/signal.mlir b/test/Dialect/LLHD/IR/signal.mlir
index 7bdfc2c466..1b1db5b7b6 100644
--- a/test/Dialect/LLHD/IR/signal.mlir
+++ b/test/Dialect/LLHD/IR/signal.mlir
@@ -63,36 +63,3 @@ func @check_drv(%sigI1 : !llhd.sig<i1>, %sigI64 : !llhd.sig<i64>, %cI1 : i1, %cI
 
   return
 }
-
-// -----
-
-// expected-error @+3 {{failed to verify that type of 'init' and underlying type of 'signal' have to match.}}
-llhd.entity @check_illegal_sig () -> () {
-  %cI1 = llhd.const 0 : i1
-  %sig1 = "llhd.sig"(%cI1) {name="foo"} : (i1) -> !llhd.sig<i32>
-}
-
-// -----
-
-// expected-error @+2 {{failed to verify that type of 'result' and underlying type of 'signal' have to match.}}
-llhd.entity @check_illegal_prb (%sig : !llhd.sig<i1>) -> () {
-  %prb = "llhd.prb"(%sig) {} : (!llhd.sig<i1>) -> i32
-}
-
-// -----
-
-// expected-error @+4 {{failed to verify that type of 'value' and underlying type of 'signal' have to match.}}
-llhd.entity @check_illegal_drv (%sig : !llhd.sig<i1>) -> () {
-  %c = llhd.const 0 : i32
-  %time = llhd.const #llhd.time<1ns, 0d, 0e> : !llhd.time
-  "llhd.drv"(%sig, %c, %time) {} : (!llhd.sig<i1>, i32, !llhd.time) -> ()
-}
-
-// -----
-
-// expected-error @+4 {{Redefinition of signal named 'sigI1'!}}
-llhd.entity @check_unique_sig_names () -> () {
-  %cI1 = llhd.const 0 : i1
-  %sig1 = llhd.sig "sigI1" %cI1 : i1
-  %sig2 = llhd.sig "sigI1" %cI1 : i1
-}
diff --git a/test/Dialect/LLHD/Transforms/processLowering.mlir b/test/Dialect/LLHD/Transforms/processLowering.mlir
index 299e7b372f..d9309be13e 100644
--- a/test/Dialect/LLHD/Transforms/processLowering.mlir
+++ b/test/Dialect/LLHD/Transforms/processLowering.mlir
@@ -44,67 +44,3 @@ llhd.proc @prbAndWaitMoreObserved(%arg0 : !llhd.sig<i64>, %arg1 : !llhd.sig<i64>
   %0 = llhd.prb %arg0 : !llhd.sig<i64>
   llhd.wait (%arg0, %arg1 : !llhd.sig<i64>, !llhd.sig<i64>), ^bb1
 }
-
-// -----
-
-// Check wait with observing probed signals
-llhd.proc @prbAndWaitNotObserved(%arg0 : !llhd.sig<i64>) -> () {
-  br ^bb1
-^bb1:
-  %0 = llhd.prb %arg0 : !llhd.sig<i64>
-  // expected-error @+1 {{Process-lowering: The wait terminator is required to have all probed signals as arguments!}}
-  llhd.wait ^bb1
-}
-
-// -----
-
-// Check that block arguments for the second block are not allowed.
-// expected-error @+1 {{Process-lowering: The second block (containing the llhd.wait) is not allowed to have arguments.}}
-llhd.proc @blockArgumentsNotAllowed(%arg0 : !llhd.sig<i64>) -> () {
-  br ^bb1(%arg0 : !llhd.sig<i64>)
-^bb1(%a : !llhd.sig<i64>):
-  llhd.wait ^bb1(%a : !llhd.sig<i64>)
-}
-
-// -----
-
-// Check that the entry block is terminated by a br terminator.
-// expected-error @+1 {{Process-lowering: The first block has to be terminated by a BranchOp from the standard dialect.}}
-llhd.proc @entryBlockMustHaveBrTerminator() -> () {
-  llhd.wait ^bb1
-^bb1:
-  llhd.wait ^bb1
-}
-
-// -----
-
-// Check that there is no optional time operand in the wait terminator.
-llhd.proc @noOptionalTime() -> () {
-  br ^bb1
-^bb1:
-  %time = llhd.const #llhd.time<0ns, 0d, 0e> : !llhd.time
-  // expected-error @+1 {{Process-lowering: llhd.wait terminators with optional time argument cannot be lowered to structural LLHD.}}
-  llhd.wait for %time, ^bb1
-}
-
-// -----
-
-// Check that if there are two blocks, the second one is terminated by a wait terminator.
-// expected-error @+1 {{Process-lowering: The second block must be terminated by a WaitOp from the LLHD dialect.}}
-llhd.proc @secondBlockTerminatedByWait() -> () {
-  br ^bb1
-^bb1:
-  llhd.halt
-}
-
-// -----
-
-// Check that there are not more than two blocks.
-// expected-error @+1 {{Process-lowering only supports processes with either one basic block terminated by a llhd.halt operation or two basic blocks where the first one contains a std.br terminator and the second one is terminated by a llhd.wait operation.}}
-llhd.proc @moreThanTwoBlocksNotAllowed() -> () {
-  br ^bb1
-^bb1:
-  br ^bb2
-^bb2:
-  llhd.wait ^bb1
-}
diff --git a/test/Dialect/LLHD/Transforms/processLoweringErrors.mlir b/test/Dialect/LLHD/Transforms/processLoweringErrors.mlir
new file mode 100644
index 0000000000..1300b7aeca
--- /dev/null
+++ b/test/Dialect/LLHD/Transforms/processLoweringErrors.mlir
@@ -0,0 +1,63 @@
+// RUN: circt-opt %s -llhd-process-lowering -split-input-file -verify-diagnostics
+
+// Check wait with observing probed signals
+llhd.proc @prbAndWaitNotObserved(%arg0 : !llhd.sig<i64>) -> () {
+  br ^bb1
+^bb1:
+  %0 = llhd.prb %arg0 : !llhd.sig<i64>
+  // expected-error @+1 {{Process-lowering: The wait terminator is required to have all probed signals as arguments!}}
+  llhd.wait ^bb1
+}
+
+// -----
+
+// Check that block arguments for the second block are not allowed.
+// expected-error @+1 {{Process-lowering: The second block (containing the llhd.wait) is not allowed to have arguments.}}
+llhd.proc @blockArgumentsNotAllowed(%arg0 : !llhd.sig<i64>) -> () {
+  br ^bb1(%arg0 : !llhd.sig<i64>)
+^bb1(%a : !llhd.sig<i64>):
+  llhd.wait ^bb1(%a : !llhd.sig<i64>)
+}
+
+// -----
+
+// Check that the entry block is terminated by a br terminator.
+// expected-error @+1 {{Process-lowering: The first block has to be terminated by a BranchOp from the standard dialect.}}
+llhd.proc @entryBlockMustHaveBrTerminator() -> () {
+  llhd.wait ^bb1
+^bb1:
+  llhd.wait ^bb1
+}
+
+// -----
+
+// Check that there is no optional time operand in the wait terminator.
+llhd.proc @noOptionalTime() -> () {
+  br ^bb1
+^bb1:
+  %time = llhd.const #llhd.time<0ns, 0d, 0e> : !llhd.time
+  // expected-error @+1 {{Process-lowering: llhd.wait terminators with optional time argument cannot be lowered to structural LLHD.}}
+  llhd.wait for %time, ^bb1
+}
+
+// -----
+
+// Check that if there are two blocks, the second one is terminated by a wait terminator.
+// expected-error @+1 {{Process-lowering: The second block must be terminated by a WaitOp from the LLHD dialect.}}
+llhd.proc @secondBlockTerminatedByWait() -> () {
+  br ^bb1
+^bb1:
+  llhd.halt
+}
+
+// -----
+
+// Check that there are not more than two blocks.
+// expected-error @+1 {{Process-lowering only supports processes with either one basic block terminated by a llhd.halt operation or two basic blocks where the first one contains a std.br terminator and the second one is terminated by a llhd.wait operation.}}
+llhd.proc @moreThanTwoBlocksNotAllowed() -> () {
+  br ^bb1
+^bb1:
+  br ^bb2
+^bb2:
+  llhd.wait ^bb1
+}
diff --git a/tools/firtool/firtool.cpp b/tools/firtool/firtool.cpp
index 883ce96f4e..3825178bc6 100644
--- a/tools/firtool/firtool.cpp
+++ b/tools/firtool/firtool.cpp
@@ -167,6 +167,7 @@ processBuffer(std::unique_ptr<llvm::MemoryBuffer> ownedBuffer,
   case OutputVerilog:
     return exportVerilog(module.get(), os);
   }
+  llvm_unreachable("invalid output format");
 };
 
 int main(int argc, char **argv) {
diff --git a/tools/llhd-sim/llhd-sim.cpp b/tools/llhd-sim/llhd-sim.cpp
index 9273eb5eb5..2bc6754983 100644
--- a/tools/llhd-sim/llhd-sim.cpp
+++ b/tools/llhd-sim/llhd-sim.cpp
@@ -20,7 +20,7 @@
 #include "mlir/Parser.h"
 #include "mlir/Pass/PassManager.h"
 #include "mlir/Support/FileUtilities.h"
-#include "mlir/Target/LLVMIR.h"
+#include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Export.h"
 #include "mlir/Transforms/Passes.h"