mirror of https://github.com/llvm/circt.git
[PyCDE] Add `.reg(clk)` method to PyCDE `Value`s
Makes it really easy to register a value.
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@ -1,6 +1,6 @@
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from typing import Type
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import circt.support as support
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import circt.dialects.hw as hw
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from circt.dialects import hw, seq
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import mlir.ir as ir
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@ -52,6 +52,9 @@ class Value:
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return Value(hw.StructExtractOp.create(self.value, attr))
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raise AttributeError(f"'Value' object has no attribute '{attr}'")
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def reg(self, clk, rst=None):
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return seq.reg(self.value, clk, rst)
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# PyCDE needs a custom version of this to support python classes.
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def var_to_attribute(obj) -> ir.Attribute:
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@ -38,6 +38,7 @@ class Top:
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@module
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class ComplexPorts:
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clk = Input(types.i1)
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sel = Input(types.i2)
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data_in = Input(dim(32, 3))
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struct_data_in = Input(types.struct({"foo": types.i32}))
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@ -49,7 +50,7 @@ class ComplexPorts:
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@generator
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def build(mod):
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return {
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'a': mod.data_in[0],
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'a': mod.data_in[0].reg(mod.clk),
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'b': mod.data_in[mod.sel],
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'c': mod.struct_data_in.foo
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}
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@ -80,9 +81,10 @@ top.print()
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sys = System([ComplexPorts])
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sys.generate()
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sys.print()
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# CHECK: hw.module @pycde.Comple_Ports(%data_in: !hw.array<3xi32>, %sel: i2, %struct_data_in: !hw.struct<foo: i32>) -> (%a: i32, %b: i32, %c: i32) {
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# CHECK: hw.module @pycde.Comple_Ports(%clk: i1, %data_in: !hw.array<3xi32>, %sel: i2, %struct_data_in: !hw.struct<foo: i32>) -> (%a: i32, %b: i32, %c: i32) {
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# CHECK: %c0_i2 = hw.constant 0 : i2
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# CHECK: [[REG0:%.+]] = hw.array_get %data_in[%c0_i2] : !hw.array<3xi32>
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# CHECK: [[REGR:%.+]] = seq.compreg [[REG0]], %clk : i32
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# CHECK: [[REG1:%.+]] = hw.array_get %data_in[%sel] : !hw.array<3xi32>
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# CHECK: [[REG2:%.+]] = hw.struct_extract %struct_data_in["foo"] : !hw.struct<foo: i32>
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# CHECK: hw.output [[REG0]], [[REG1]], [[REG2]] : i32, i32, i32
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# CHECK: hw.output [[REGR]], [[REG1]], [[REG2]] : i32, i32, i32
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