mirror of https://github.com/llvm/circt.git
[FIRRTL] Parse params < 32-bit as 32-bit (#2300)
Change FIRRTL parsing to convert all parameters less than 32-bit to 32-bit APInts. This fixes downstream issues with Verilog emission, where negative parameters may have too few bits in their APInt representation and print as shorter-than-expected literals. Fixes #2299. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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@ -3404,6 +3404,11 @@ ParseResult FIRCircuitParser::parseModule(CircuitOp circuit,
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if (parseIntLit(result, "invalid integer parameter"))
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if (parseIntLit(result, "invalid integer parameter"))
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return failure();
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return failure();
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// If the integer parameter is less than 32-bits, sign extend this to a
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// 32-bit value. This needs to eventually emit as a 32-bit value in
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// Verilog and we want to get the size correct immediately.
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result = result.sextOrSelf(32);
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value = builder.getIntegerAttr(
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value = builder.getIntegerAttr(
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builder.getIntegerType(result.getBitWidth()), result);
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builder.getIntegerType(result.getBitWidth()), result);
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break;
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break;
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@ -0,0 +1,18 @@
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; RUN: firtool -split-input-file -verilog %s | FileCheck %s
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; Test that a negative parameter prints out as a 32-bit parameter. It is fine
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; to change this test to print as "-1" in the output Verilog, but not as a
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; non-32-bit "-1" like "0xF".
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circuit NegativeParameter:
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extmodule Foo:
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output a: UInt<1>
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parameter x = -1
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module NegativeParameter:
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output a: UInt<1>
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inst foo of Foo
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a <= foo.a
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; CHECK-LABEL: module NegativeParameter
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; CHECK: Foo #(
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; CHECK-NEXT: .x(4294967295)
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@ -32,7 +32,7 @@ circuit MyModule : ; CHECK: firrtl.circuit "MyModule" {
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; CHECK: parameters = {DEFAULT = 0 : i32,
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; CHECK: parameters = {DEFAULT = 0 : i32,
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; CHECK: DEPTH = 3.242000e+01 : f64,
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; CHECK: DEPTH = 3.242000e+01 : f64,
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; CHECK: FORMAT = "xyz_timeout=%d\0A",
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; CHECK: FORMAT = "xyz_timeout=%d\0A",
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; CHECK: WIDTH = 32 : i8}}
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; CHECK: WIDTH = 32 : i32}}
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; CHECK-NOT: {
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; CHECK-NOT: {
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extmodule MyParameterizedExtModule :
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extmodule MyParameterizedExtModule :
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input in: UInt
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input in: UInt
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@ -576,7 +576,7 @@ circuit MyModule : ; CHECK: firrtl.circuit "MyModule" {
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; CHECK: %c-4_si4 = firrtl.constant -4 : !firrtl.sint<4>
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; CHECK: %c-4_si4 = firrtl.constant -4 : !firrtl.sint<4>
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; CHECK-LABEL: firrtl.extmodule @issue183()
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; CHECK-LABEL: firrtl.extmodule @issue183()
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; CHECK: attributes {parameters = {A = -1 : i4}}
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; CHECK: attributes {parameters = {A = -1 : i32}}
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extmodule issue183:
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extmodule issue183:
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parameter A = -1
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parameter A = -1
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