mirror of https://github.com/llvm/circt.git
[FIRRTL] Remove support for circt.Intrinsic annotation. (#6857)
Documentation indicates this was intended to be removed once FIRRTL language supports intrinsics, and we have intmodule's now.
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@ -858,19 +858,6 @@ Example:
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}
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```
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### circt.Intrinsic
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| Property | Type | Description |
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| ---------- | ------ | ------------- |
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| class | string | `circt.Intrinsic` |
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| target | string | Reference target |
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| intrinsic | string | Name of Intrinsic |
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Used to indicate an external module is really an intrinsic module. This exists
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to allow a frontend to generate intrinsics without FIRRTL language support for
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intrinsics. It is expected this will be deprecated as soon as the FIRRTL language
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supports intrinsics. This annotation can only be local and applied to a module.
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### SitestBlackBoxAnnotation
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| Property | Type | Description |
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@ -118,7 +118,6 @@ LogicalResult IntrinsicLowerings::lower(CircuitOp circuit,
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bool allowUnknownIntrinsics) {
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unsigned numFailures = 0;
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for (auto op : llvm::make_early_inc_range(circuit.getOps<FModuleLike>())) {
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StringAttr intname;
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if (auto extMod = dyn_cast<FExtModuleOp>(*op)) {
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// Special-case some extmodules, identifying them by name.
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auto it = extmods.find(extMod.getDefnameAttr());
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@ -129,27 +128,18 @@ LogicalResult IntrinsicLowerings::lower(CircuitOp circuit,
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} else {
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++numFailures;
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}
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continue;
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}
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continue;
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}
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// Otherwise, find extmodules which have an intrinsic annotation.
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auto anno = AnnotationSet(&*op).getAnnotation("circt.Intrinsic");
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if (!anno)
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continue;
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intname = anno.getMember<StringAttr>("intrinsic");
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if (!intname) {
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op.emitError("intrinsic annotation with no intrinsic name");
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++numFailures;
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continue;
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}
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} else if (auto intMod = dyn_cast<FIntModuleOp>(*op)) {
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intname = intMod.getIntrinsicAttr();
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if (!intname) {
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op.emitError("intrinsic module with no intrinsic name");
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++numFailures;
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continue;
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}
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} else {
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auto intMod = dyn_cast<FIntModuleOp>(*op);
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if (!intMod)
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continue;
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auto intname = intMod.getIntrinsicAttr();
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if (!intname) {
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op.emitError("intrinsic module with no intrinsic name");
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++numFailures;
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continue;
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}
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@ -414,7 +414,6 @@ static llvm::StringMap<AnnoRecord> annotationRecords{{
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{"circt.testLocalOnly", {stdResolve, applyWithoutTarget<>}},
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{"circt.testNT", {noResolve, applyWithoutTarget<>}},
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{"circt.missing", {tryResolve, applyWithoutTarget<true>}},
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{"circt.Intrinsic", {stdResolve, applyWithoutTarget<false, FExtModuleOp>}},
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// Grand Central Views/Interfaces Annotations
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{extractGrandCentralClass, NoTargetAnnotation},
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{grandCentralHierarchyFileAnnoClass, NoTargetAnnotation},
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@ -3,46 +3,7 @@
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// CHECK-LABEL: "Foo"
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firrtl.circuit "Foo" {
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// CHECK-NOT: NameDoesNotMatter
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firrtl.extmodule @NameDoesNotMatter(in i : !firrtl.clock, out size : !firrtl.uint<32>) attributes
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{annotations = [{class = "circt.Intrinsic", intrinsic = "circt.sizeof"}]}
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// CHECK-NOT: NameDoesNotMatter2
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firrtl.extmodule @NameDoesNotMatter2(in i : !firrtl.clock, out found : !firrtl.uint<1>) attributes
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{annotations = [{class = "circt.Intrinsic", intrinsic = "circt.isX"}]}
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// CHECK-NOT: NameDoesNotMatter3
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firrtl.extmodule @NameDoesNotMatter3<FORMAT: none = "foo">(out found : !firrtl.uint<1>) attributes
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{annotations = [{class = "circt.Intrinsic", intrinsic = "circt.plusargs.test"}]}
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// CHECK-NOT: NameDoesNotMatter4
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firrtl.extmodule @NameDoesNotMatter4<FORMAT: none = "foo">(out found : !firrtl.uint<1>, out result: !firrtl.uint<5>) attributes
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{annotations = [{class = "circt.Intrinsic", intrinsic = "circt.plusargs.value"}]}
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// CHECK: Foo
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firrtl.module @Foo(in %clk : !firrtl.clock, out %s : !firrtl.uint<32>, out %io1 : !firrtl.uint<1>, out %io2 : !firrtl.uint<1>, out %io3 : !firrtl.uint<1>, out %io4 : !firrtl.uint<5>) {
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%i1, %size = firrtl.instance "" @NameDoesNotMatter(in i : !firrtl.clock, out size : !firrtl.uint<32>)
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// CHECK-NOT: NameDoesNotMatter
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// CHECK: firrtl.int.sizeof
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firrtl.strictconnect %i1, %clk : !firrtl.clock
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firrtl.strictconnect %s, %size : !firrtl.uint<32>
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%i2, %found2 = firrtl.instance "" @NameDoesNotMatter2(in i : !firrtl.clock, out found : !firrtl.uint<1>)
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// CHECK-NOT: NameDoesNotMatter2
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// CHECK: firrtl.int.isX
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firrtl.strictconnect %i2, %clk : !firrtl.clock
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firrtl.strictconnect %io1, %found2 : !firrtl.uint<1>
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%found3 = firrtl.instance "" @NameDoesNotMatter3(out found : !firrtl.uint<1>)
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// CHECK-NOT: NameDoesNotMatter3
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// CHECK: firrtl.int.plusargs.test "foo"
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firrtl.strictconnect %io2, %found3 : !firrtl.uint<1>
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%found4, %result1 = firrtl.instance "" @NameDoesNotMatter4(out found : !firrtl.uint<1>, out result: !firrtl.uint<5>)
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// CHECK-NOT: NameDoesNotMatter4
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// CHECK: firrtl.int.plusargs.value "foo" : !firrtl.uint<5>
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firrtl.strictconnect %io3, %found4 : !firrtl.uint<1>
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firrtl.strictconnect %io4, %result1 : !firrtl.uint<5>
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}
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// CHECK-NOT: NameDoesNotMatte5
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// CHECK-NOT: NameDoesNotMatter5
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firrtl.intmodule @NameDoesNotMatter5(in i : !firrtl.clock, out size : !firrtl.uint<32>) attributes
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{intrinsic = "circt.sizeof"}
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// CHECK-NOT: NameDoesNotMatter6
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@ -55,8 +16,8 @@ firrtl.circuit "Foo" {
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firrtl.intmodule @NameDoesNotMatter8<FORMAT: none = "foo">(out found : !firrtl.uint<1>, out result: !firrtl.uint<5>) attributes
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{intrinsic = "circt.plusargs.value"}
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// CHECK: Bar
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firrtl.module @Bar(in %clk : !firrtl.clock, out %s : !firrtl.uint<32>, out %io1 : !firrtl.uint<1>, out %io2 : !firrtl.uint<1>, out %io3 : !firrtl.uint<1>, out %io4 : !firrtl.uint<5>) {
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// CHECK: Foo
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firrtl.module @Foo(in %clk : !firrtl.clock, out %s : !firrtl.uint<32>, out %io1 : !firrtl.uint<1>, out %io2 : !firrtl.uint<1>, out %io3 : !firrtl.uint<1>, out %io4 : !firrtl.uint<5>) {
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%i1, %size = firrtl.instance "" @NameDoesNotMatter5(in i : !firrtl.clock, out size : !firrtl.uint<32>)
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// CHECK-NOT: NameDoesNotMatter5
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// CHECK: firrtl.int.sizeof
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@ -81,19 +42,11 @@ firrtl.circuit "Foo" {
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firrtl.strictconnect %io4, %result1 : !firrtl.uint<5>
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}
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// CHECK-NOT: ClockGate0
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// CHECK-NOT: ClockGate1
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firrtl.extmodule @ClockGate0(in in: !firrtl.clock, in en: !firrtl.uint<1>, out out: !firrtl.clock) attributes {annotations = [{class = "circt.Intrinsic", intrinsic = "circt.clock_gate"}]}
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firrtl.intmodule @ClockGate1(in in: !firrtl.clock, in en: !firrtl.uint<1>, out out: !firrtl.clock) attributes {intrinsic = "circt.clock_gate"}
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// CHECK: ClockGate
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firrtl.module @ClockGate(in %clk: !firrtl.clock, in %en: !firrtl.uint<1>) {
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// CHECK-NOT: ClockGate0
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// CHECK: firrtl.int.clock_gate
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%in1, %en1, %out1 = firrtl.instance "" @ClockGate0(in in: !firrtl.clock, in en: !firrtl.uint<1>, out out: !firrtl.clock)
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firrtl.strictconnect %in1, %clk : !firrtl.clock
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firrtl.strictconnect %en1, %en : !firrtl.uint<1>
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// CHECK-NOT: ClockGate1
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// CHECK: firrtl.int.clock_gate
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%in2, %en2, %out2 = firrtl.instance "" @ClockGate1(in in: !firrtl.clock, in en: !firrtl.uint<1>, out out: !firrtl.clock)
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@ -101,18 +54,11 @@ firrtl.circuit "Foo" {
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firrtl.strictconnect %en2, %en : !firrtl.uint<1>
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}
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// CHECK-NOT: ClockInverter0
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// CHECK-NOT: ClockInverter1
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firrtl.extmodule @ClockInverter0(in in: !firrtl.clock, out out: !firrtl.clock) attributes {annotations = [{class = "circt.Intrinsic", intrinsic = "circt.clock_inv"}]}
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firrtl.intmodule @ClockInverter1(in in: !firrtl.clock, out out: !firrtl.clock) attributes {intrinsic = "circt.clock_inv"}
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// CHECK: ClockInverter
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firrtl.module @ClockInverter(in %clk: !firrtl.clock) {
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// CHECK-NOT: ClockInverter0
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// CHECK: firrtl.int.clock_inv
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%in1, %out1 = firrtl.instance "" @ClockInverter0(in in: !firrtl.clock, out out: !firrtl.clock)
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firrtl.strictconnect %in1, %clk : !firrtl.clock
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// CHECK-NOT: ClockInverter1
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// CHECK: firrtl.int.clock_inv
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%in2, %out2 = firrtl.instance "" @ClockInverter1(in in: !firrtl.clock, out out: !firrtl.clock)
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@ -203,7 +149,7 @@ firrtl.circuit "Foo" {
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%cover.property = firrtl.instance "cover" @VerifCover(in property: !firrtl.uint<1>)
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}
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firrtl.extmodule @Mux2Cell(in sel: !firrtl.uint<1>, in high: !firrtl.uint, in low: !firrtl.uint, out out: !firrtl.uint) attributes {annotations = [{class = "circt.Intrinsic", intrinsic = "circt.mux2cell"}]}
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firrtl.intmodule @Mux2Cell(in sel: !firrtl.uint<1>, in high: !firrtl.uint, in low: !firrtl.uint, out out: !firrtl.uint) attributes {intrinsic = "circt.mux2cell"}
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firrtl.intmodule @Mux4Cell(in sel: !firrtl.uint<2>, in v3: !firrtl.uint, in v2: !firrtl.uint, in v1: !firrtl.uint, in v0: !firrtl.uint, out out: !firrtl.uint) attributes {intrinsic = "circt.mux4cell"}
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// CHECK: firrtl.module @MuxCell()
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