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[SV] Switch LocalParamOp to take an attribute instead of SSA value. 

This keeps params and attributes in different domains.  This will
allow better enforcement of valid parameter values in the verifier.
This commit is contained in:
Chris Lattner 2021-09-19 12:33:01 -07:00
parent 0f7bb1b2ce
commit e1e7e0feaf
4 changed files with 12 additions and 16 deletions
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11
include/circt/Dialect/SV/SVExpressions.td
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@ -95,20 +95,17 @@ def ConstantZOp : SVOp<"constantZ", [NoSideEffect, HasCustomSSAName]> {
}
def LocalParamOp : SVOp<"localparam",
[SameOperandsAndResultType, NoSideEffect, HasCustomSSAName]> {
[FirstAttrDerivedResultType, NoSideEffect, HasCustomSSAName]> {
let summary = "Declare a localparam";
let description = [{
The localparam operation produces a `localparam` declaration. See SV spec
6.20.4 p125.
```
%result = hw.localparam %input : t1
```
}];
let arguments = (ins StrAttr:$name, HWIntegerType:$input);
let results = (outs HWIntegerType:$result);
let arguments = (ins AnyAttr:$value, StrAttr:$name);
let results = (outs HWValueType:$result);
let assemblyFormat = [{
custom<ImplicitSSAName>(attr-dict) $input `:` type($result)
`:` type($result) custom<ImplicitSSAName>(attr-dict)
}];
}

2
lib/Translation/ExportVerilog/ExportVerilog.cpp
View File

@ -2860,7 +2860,7 @@ void StmtEmitter::collectNamesEmitDecls(Block &block) {
if (auto localparam = dyn_cast<LocalParamOp>(op)) {
os << " = ";
emitExpression(localparam.input(), opsForLocation, ForceEmitMultiUse);
printParamValue(localparam.value(), op, localparam.name(), os);
}
// Constants carry their assignment directly in the declaration.

6
test/Dialect/SV/basic.mlir
View File

@ -4,9 +4,9 @@
// CHECK-LABEL: hw.module @test1(%arg0: i1, %arg1: i1, %arg8: i8) {
hw.module @test1(%arg0: i1, %arg1: i1, %arg8: i8) {
%c11_i42 = hw.constant 11: i42
// CHECK: %param_x = sv.localparam %c11_i42 : i42
%param_x = sv.localparam %c11_i42 : i42
// CHECK: %param_x = sv.localparam : i42 {value = 11 : i42}
%param_x = sv.localparam : i42 {value = 11 : i42}
// This corresponds to this block of system verilog code:
// always @(posedge arg0) begin

9
test/ExportVerilog/sv-dialect.mlir
View File

@ -6,12 +6,11 @@ hw.module @M1(%clock : i1, %cond : i1, %val : i8) {
%forceWire = sv.wire : !hw.inout<i1>
%c11_i42 = hw.constant 11: i42
// CHECK: localparam [41:0] param_x = 42'hB;
%param_x = sv.localparam %c11_i42 : i42
// CHECK: localparam [41:0] param_x = 42'd11;
%param_x = sv.localparam : i42 { value = 11: i42 }
%param_tmp = comb.add %param_x, %c11_i42 : i42
// CHECK: localparam [41:0] param_y = param_x + 42'hB;
%param_y = sv.localparam %param_tmp : i42
// CHECK: localparam [41:0] param_y = 42'd4;
%param_y = sv.localparam : i42 { value = 4: i42 }
// CHECK: always @(posedge clock) begin
sv.always posedge %clock {