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[integration-test] Properly init a reg, fixing Issue #1188.

This commit is contained in:
Chris Lattner 2021-06-02 12:19:54 -07:00
parent 99ce0d3285
commit d7cca9529f
1 changed files with 1 additions and 1 deletions
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integration_test/EmitVerilog/exampleCodeGen.fir
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@ -10,7 +10,7 @@ circuit top :
output io_out3 : UInt<3>
reg D0123456 : UInt<6>, clock with :
reset => (UInt<1>("h0"), D0123456) @[main.scala 16:25]
reset => (reset, UInt<6>("h0")) @[main.scala 16:25]
node _T = bits(D0123456, 4, 0) @[main.scala 20:30]
node _T_1 = bits(D0123456, 5, 5) @[main.scala 20:47]
node _T_2 = cat(_T, _T_1) @[main.scala 20:36]