[NFC] Added newlines to the end of files

.clang-format

@@ -1,2 +1,2 @@
 BasedOnStyle: LLVM
-AlwaysBreakTemplateDeclarations: Yes
+AlwaysBreakTemplateDeclarations: Yes

include/circt/Dialect/FIRRTL/CHIRRTLDialect.h

@@ -33,4 +33,4 @@
 #define GET_OP_CLASSES
 #include "circt/Dialect/FIRRTL/CHIRRTL.h.inc"
 
-#endif // CIRCT_DIALECT_FIRRTL_CHIRRTLDIALECT_H
+#endif // CIRCT_DIALECT_FIRRTL_CHIRRTLDIALECT_H

include/circt/Dialect/FIRRTL/CHIRRTLVisitors.h

@@ -65,4 +65,4 @@ public:
 } // namespace chirrtl
 } // namespace circt
 
-#endif // CIRCT_DIALECT_FIRRTL_CHIRRTLVISITORS_H
+#endif // CIRCT_DIALECT_FIRRTL_CHIRRTLVISITORS_H

include/circt/Dialect/FIRRTL/CMakeLists.txt

@@ -27,4 +27,4 @@ add_dependencies(circt-headers CIRCTFIRRTLOpInterfacesIncGen)
 
 # CHIRRTL
 add_circt_dialect(CHIRRTL chirrtl CHIRRTL)
-add_circt_doc(CHIRRTL -gen-dialect-doc CHIRRTL Dialects/)
+add_circt_doc(CHIRRTL -gen-dialect-doc CHIRRTL Dialects/)

include/circt/Dialect/FIRRTL/FIRRTLUtils.h

@@ -24,4 +24,4 @@ void emitConnect(ImplicitLocOpBuilder &builder, Value lhs, Value rhs);
 } // namespace firrtl
 } // namespace circt
 
-#endif // CIRCT_DIALECT_FIRRTL_FIRRTLUTILS_H
+#endif // CIRCT_DIALECT_FIRRTL_FIRRTLUTILS_H

lib/Conversion/ExportVerilog/RearrangableOStream.cpp

@@ -185,4 +185,4 @@ void RearrangableOStream::write_impl(const char *ptr, size_t size) {
   memcpy(remainingChunkPtr, ptr, size);
   remainingChunkPtr += size;
   remainingChunkSize -= size;
-}
+}

lib/Dialect/Comb/CombAnalysis.cpp

@@ -86,4 +86,4 @@ static KnownBits computeKnownBits(Value v, unsigned depth) {
 /// constant" always returns zeros for the zero bits in a constant.
 KnownBits comb::computeKnownBits(Value value) {
   return ::computeKnownBits(value, 0);
-}
+}

lib/Dialect/LLHD/CMakeLists.txt

@@ -1,3 +1,3 @@
 add_subdirectory(IR)
 add_subdirectory(Simulator)
-add_subdirectory(Transforms)
+add_subdirectory(Transforms)

test/Conversion/ExportVerilog/hw-typedecls.mlir

@@ -86,4 +86,4 @@ hw.module @testAggregateInout(%i: i1) -> (out1: i8, out2: i1) {
   %2 = sv.read_inout %0 : !hw.inout<i8>
   %3 = sv.read_inout %1 : !hw.inout<i1>
   hw.output %2, %3 : i8, i1
-}
+}

test/Conversion/HandshakeToFIRRTL/test_select.mlir

@@ -40,4 +40,4 @@
 handshake.func @test_select(%arg0: i1, %arg1: i32, %arg2: i32, %arg3: none, ...) -> (i32, none) {
   %0 = select %arg0, %arg1, %arg2 : i32
   return %0, %arg3 : i32, none
-}
+}

test/Conversion/HandshakeToHW/test_simple_loop.mlir

@@ -70,4 +70,4 @@ handshake.func @main(%arg0: none, ...) -> (i64, none) attributes {argNames = ["i
   %14:2 = fork [2] %trueResult_0 : i64
   %15 = arith.addi %trueResult_4, %14#1 : i64
   return %falseResult_5, %falseResult_3 : i64, none
-}
+}

test/Conversion/StandardToHandshake/errors.mlir

@@ -43,4 +43,4 @@ func @non_canon_loop(%arg0 : memref<100xi32>, %arg1 : i32) -> i32 {
   cf.br ^bb1(%3 : index)
 ^bb3:  // pred: ^bb1
   return %c0_i32 : i32
-}
+}

test/Dialect/FIRRTL/dedup-errors.mlir

@@ -30,4 +30,4 @@ firrtl.circuit "MustDedup" attributes {annotations = [{
     firrtl.instance test0 @Test0(in i : !firrtl.uint<1>)
     firrtl.instance test1 @Test1(in i : !firrtl.uint<8>)
   }
-}
+}

test/Dialect/FIRRTL/dedup-locations.mlir

@@ -15,4 +15,4 @@ firrtl.module @Test() {
   firrtl.instance dedup0 @Dedup0()
   firrtl.instance dedup1 @Dedup1()
 }
-}
+}

test/Dialect/FIRRTL/expand-whens-errors.mlir

@@ -128,4 +128,4 @@ firrtl.circuit "CheckInitialization" {
 firrtl.module @CheckInitialization(in %p : !firrtl.uint<1>, out %out: !firrtl.vector<bundle<a:uint<1>, b:uint<1>>, 1>) {
   // expected-error @-1 {{sink "out[0].a" not fully initialized}}
 }
-}
+}

test/Dialect/FIRRTL/expand-whens-locations.mlir

@@ -47,4 +47,4 @@ firrtl.module @Nested(in %p: !firrtl.uint<1>, in %v0: !firrtl.uint<8>, in %v1: !
   // CHECK: firrtl.connect %out, [[OUTSIDE]]
   // CHECK-SAME: loc("outside")
 }
-}
+}

test/Dialect/FIRRTL/imconstprop-aggregate.mlir

@@ -390,4 +390,4 @@ firrtl.circuit "dntOutput"  {
     %0 = firrtl.subfield %b(0) : (!firrtl.bundle<v: uint<3>>) -> !firrtl.uint<3>
     firrtl.strictconnect %0, %c1_ui3 : !firrtl.uint<3>
   }
-}
+}

test/Dialect/FIRRTL/lower-types-aggregate.mlir

@@ -10,4 +10,4 @@ firrtl.circuit "TopLevel" {
   firrtl.module @TopLevel(in %source: !firrtl.bundle<valid: uint<1>>,
                           out %sink: !firrtl.bundle<valid: uint<1>>) {
   }
-}
+}

test/Dialect/FIRRTL/parse-basic.fir

@@ -1083,4 +1083,4 @@ circuit MyModule :     ; CHECK: firrtl.circuit "MyModule" {
     ; CHECK: !chirrtl.cmemory<vector<uint<8>, 16>, 34359738368>
     smem testharness : UInt<8>[16] [34359738368]
     node w_addr = UInt<36>(42) @[Cat.scala 31:58]
-    write mport MPORT = testharness[w_addr], clock
+    write mport MPORT = testharness[w_addr], clock

test/Dialect/FIRRTL/remove-unused-ports.mlir

@@ -136,4 +136,4 @@ firrtl.circuit "Top"   {
     firrtl.strictconnect %A_b, %b : !firrtl.uint<1>
     firrtl.strictconnect %c, %A_c : !firrtl.uint<1>
   }
-}
+}

test/Dialect/Handshake/remove_buffers.mlir

@@ -12,4 +12,4 @@ handshake.func @simple_c(%arg0: i32, %arg1: i32, %arg2: none) -> (i32, none) {
   %3 = buffer [2] seq %2 : i32
   %4 = buffer [2] seq %arg2 : none
   return %3, %4 : i32, none
-}
+}

test/circt-reduce/memory-stubber.mlir

@@ -19,4 +19,4 @@ firrtl.circuit "Basic"   {
     // CHECK: [[SINT:%.+]] = firrtl.asSInt {{%.+}}
     // CHECK: firrtl.connect {{%.+}}, [[SINT]]
   }
-}
+}

test/firtool/firtool.fir

@@ -255,4 +255,4 @@ circuit test_mod : %[[{"a": "a"}]]
     input in : UInt<1>
     output out : UInt<1>
     out is invalid
-; VERILOG-LABEL: module UnusedPortsMod();
+; VERILOG-LABEL: module UnusedPortsMod();

test/firtool/optimizations.mlir

@@ -18,4 +18,4 @@ hw.module @Issue2393(%clock: i1, %c: i1, %data: i2) {
   // CHECK-NEXT:     r2 <= data;
   // CHECK-NEXT:   end
   // CHECK-NEXT: end
-}
+}

test/lib/Analysis/CMakeLists.txt

@@ -0,0 +1 @@
+