Intel tools for integration tests (#683)

Intel tools for integration tests
Intel tools include a stripped down questa flavor too.

CMakeLists.txt

@@ -152,6 +152,31 @@ else()
   endif()
 endif()
 
+#-------------------------------------------------------------------------------
+# Quartus Configuration
+#-------------------------------------------------------------------------------
+
+# If Quartus hasn't been explicitly disabled, find it.
+option(QUARTUS_DISABLE "Disable the Quartus synthesis tests.")
+if (QUARTUS_DISABLE)
+  message(STATUS "Disabling Quartus tests.")
+else()
+  if (EXISTS ${QUARTUS_PATH})
+    message(STATUS "Setting Quartus path to ${QUARTUS_PATH}.")
+  else()
+    # Search for Quartus's `quartus` command.
+    find_program(QUARTUS_PATH "quartus")
+    if(EXISTS ${QUARTUS_PATH})
+      # Then strip the filename.
+      get_filename_component(QUARTUS_PATH ${QUARTUS_PATH} DIRECTORY)
+      message(STATUS "Found Quartus at ${QUARTUS_PATH}.")
+    else()
+      set(QUARTUS_PATH "")
+      message(STATUS "Did not find Quartus.")
+    endif()
+  endif()
+endif()
+
 #-------------------------------------------------------------------------------
 # Questa Configuration
 #-------------------------------------------------------------------------------

integration_test/EmitVerilog/standards.mlir

@@ -1,4 +1,5 @@
-// REQUIRES: verilator
+// REQUIRES: verilator, questa
+
 // RUN: firtool --lower-to-rtl --verilog %s > %t1.1995.v
 // RUN: firtool --lower-to-rtl --verilog %s > %t1.2001.v
 // RUN: firtool --lower-to-rtl --verilog %s > %t1.2005.v
@@ -6,6 +7,7 @@
 // RUN: firtool --lower-to-rtl --verilog %s > %t1.2009.sv
 // RUN: firtool --lower-to-rtl --verilog %s > %t1.2012.sv
 // RUN: firtool --lower-to-rtl --verilog %s> %t1.2017.sv
+
 // RUN: verilator --lint-only +1364-1995ext+v %t1.1995.v || true
 // RUN: verilator --lint-only +1364-2001ext+v %t1.2001.v || true
 // RUN: verilator --lint-only +1364-2005ext+v %t1.2005.v || true
@@ -14,6 +16,14 @@
 // RUN: verilator --lint-only +1800-2012ext+sv %t1.2012.sv
 // RUN: verilator --lint-only +1800-2017ext+sv %t1.2017.sv
 
+// RUN: vlog -lint %t1.1995.v -vlog95compat || true
+// RUN: vlog -lint %t1.2001.v -vlog01compat || true
+// RUN: vlog -lint %t1.2005.v || true
+// RUN: vlog -lint -sv -sv05compat %t1.2005.sv
+// RUN: vlog -lint -sv -sv09compat %t1.2009.sv
+// RUN: vlog -lint -sv -sv12compat %t1.2012.sv
+// RUN: vlog -lint -sv -sv17compat %t1.2017.sv
+
 rtl.module @top(%clock : i1, %reset: i1,
                 %a: i4, 
                 %s: !rtl.struct<foo: i2, bar: i4>,

integration_test/lit.cfg.py

@@ -84,6 +84,12 @@ if config.verilator_path != "":
   llvm_config.with_environment(
       'VERILATOR_PATH', config.verilator_path)
 
+# Enable Questa if it has been detected.
+if config.quartus_path != "":
+  tool_dirs.append(os.path.dirname(config.quartus_path))
+  tools.append('quartus')
+  config.available_features.add('quartus')
+
 # Enable Questa if it has been detected.
 if config.questa_path != "":
   config.available_features.add('questa')

integration_test/lit.site.cfg.py.in

@@ -40,6 +40,7 @@ config.verilator_path = "@VERILATOR_PATH@"
 config.esi_cosim_path = "@ESI_COSIM_PATH@"
 config.timeout = "@CIRCT_INTEGRATION_TIMEOUT@"
 config.yosys_path = "@YOSYS_PATH@"
+config.quartus_path = "@QUARTUS_PATH@"
 config.questa_path = "@QUESTA_PATH@"
 config.esi_capnp = "@ESI_CAPNP@"