mirror of https://github.com/llvm/circt.git
Always_ff support with explicit resets and reset style (sync/async) (#491)
Always_ff support with explicit resets and reset style (sync/async). Reset blocks are tracked as part of this node to simplify merging always blocks with similar style resets. Keeping different always blocks for different reset styles of registers is driven from tool requirements and style guidelines.
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@ -138,6 +138,60 @@ def AlwaysOp : SVOp<"always", [HasRegionTerminator, NoRegionArguments,
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let verifier = "return ::verifyAlwaysOp(*this);";
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}
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def NoReset: I32EnumAttrCase<"NoReset", 0, "noreset">;
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def SyncReset: I32EnumAttrCase<"SyncReset", 1, "syncreset">;
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def AsyncReset: I32EnumAttrCase<"AsyncReset", 2, "asyncreset">;
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def ResetTypeAttr : I32EnumAttr<"ResetType", "reset type",
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[NoReset, SyncReset, AsyncReset]>;
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def AlwaysFFOp : SVOp<"alwaysff", [HasRegionTerminator, NoRegionArguments,
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RecursiveSideEffects]> {
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let summary = "'alwaysff @' block with optional reset";
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let description = [{
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alwaysff blocks represent always_ff verilog nodes, which enforce inference
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of registers. This block takes a clock signal and edge sensitivity and
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reset type. If the reset type is anything but 'noreset', the block takes a
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reset signal, reset sensitivity, and reset block. Appropriate if conditions
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are generated in the output code based on the reset type. A negative-edge,
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asynchronous reset will check the inverse of the reset condition
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(if (!reset) begin resetblock end) to match the sensitivity.
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}];
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let regions = (region SizedRegion<1>:$bodyBlk, AnyRegion:$resetBlk);
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let arguments = (ins EventControlAttr:$clockEdge, I1:$clock,
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DefaultValuedAttr<ResetTypeAttr, "0">:$resetStyle,
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OptionalAttr<EventControlAttr>:$resetEdge,
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Optional<I1>:$reset);
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let results = (outs);
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let assemblyFormat = [{
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$clockEdge `,` $clock
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( `,` $resetStyle `,` $resetEdge^ `,` $reset $resetBlk )? $bodyBlk attr-dict
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}];
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let skipDefaultBuilders = 1;
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let builders = [
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OpBuilderDAG<(ins "EventControl":$clockEdge, "Value":$clock,
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CArg<"std::function<void()>", "{}">:$bodyCtor)>,
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OpBuilderDAG<(ins "EventControl":$clockEdge, "Value":$clock,
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"ResetType":$resetStyle,
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"EventControl":$resetEdge, "Value":$reset,
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CArg<"std::function<void()>", "{}">:$resetCtor,
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CArg<"std::function<void()>", "{}">:$bodyCtor)>
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];
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let extraClassDeclaration = [{
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Block *getBodyBlock() { return &bodyBlk().front(); }
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Block *getResetBlock() { return &resetBlk().front(); }
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}];
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// Check that we have the same number of events and conditions.
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//let verifier = "return ::verifyAlwaysOp(*this);";
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}
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def InitialOp : SVOp<"initial", [HasRegionTerminator, NoRegionArguments,
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RecursiveSideEffects]> {
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let summary = "'initial' block";
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@ -167,7 +221,8 @@ def InitialOp : SVOp<"initial", [HasRegionTerminator, NoRegionArguments,
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def YieldOp
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: SVOp<"yield", [NoSideEffect, Terminator,
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ParentOneOf<["IfDefOp, IfOp", "AlwaysOp", "InitialOp"]>]> {
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ParentOneOf<["IfDefOp, IfOp", "AlwaysOp", "InitialOp",
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"AlwaysFFOp"]>]> {
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let summary = "terminator for control-flow operation regions";
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let arguments = (ins);
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@ -30,7 +30,7 @@ public:
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// Declarations.
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RegOp,
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// Control flow.
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IfDefOp, IfOp, AlwaysOp, InitialOp,
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IfDefOp, IfOp, AlwaysOp, AlwaysFFOp, InitialOp,
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// Other Statements.
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YieldOp, BPAssignOp, PAssignOp, AliasOp, FWriteOp,
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FatalOp, FinishOp, VerbatimOp,
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@ -75,6 +75,7 @@ public:
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HANDLE(IfDefOp, Unhandled);
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HANDLE(IfOp, Unhandled);
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HANDLE(AlwaysOp, Unhandled);
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HANDLE(AlwaysFFOp, Unhandled);
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HANDLE(InitialOp, Unhandled);
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// Other Statements.
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@ -1941,13 +1941,13 @@ LogicalResult FIRRTLLowering::visitStmt(ConnectOp op) {
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if (!clockVal)
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return failure();
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builder->create<sv::AlwaysOp>(EventControl::AtPosEdge, clockVal, [&]() {
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builder->create<sv::AlwaysFFOp>(EventControl::AtPosEdge, clockVal, [&]() {
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builder->create<sv::PAssignOp>(destVal, srcVal);
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});
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return success();
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}
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// If this is an assignment to a RegInit, then the connect implicitly
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// If this is an assignment to a RegReset, then the connect implicitly
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// happens under the clock and reset that gate the register.
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if (auto regResetOp = dyn_cast_or_null<RegResetOp>(dest.getDefiningOp())) {
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Value clockVal = getLoweredValue(regResetOp.clockVal());
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@ -1955,24 +1955,16 @@ LogicalResult FIRRTLLowering::visitStmt(ConnectOp op) {
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if (!clockVal || !resetSignal)
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return failure();
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auto one = builder->create<rtl::ConstantOp>(APInt(1, 1));
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auto invResetSignal = builder->create<rtl::XorOp>(resetSignal, one);
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// auto one = builder->create<rtl::ConstantOp>(APInt(1, 1));
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// auto invResetSignal = builder->create<rtl::XorOp>(resetSignal, one);
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auto resetFn = [&]() {
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builder->create<sv::IfOp>(invResetSignal, [&]() {
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builder->create<sv::PAssignOp>(destVal, srcVal);
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});
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};
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if (regResetOp.resetSignal().getType().isa<AsyncResetType>()) {
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builder->create<sv::AlwaysOp>(
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ArrayRef<EventControl>{EventControl::AtPosEdge,
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EventControl::AtPosEdge},
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ArrayRef<Value>{clockVal, resetSignal}, resetFn);
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return success();
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} else { // sync reset
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builder->create<sv::AlwaysOp>(EventControl::AtPosEdge, clockVal, resetFn);
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}
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builder->create<sv::AlwaysFFOp>(
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EventControl::AtPosEdge, clockVal,
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regResetOp.resetSignal().getType().isa<AsyncResetType>()
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? ::ResetType::AsyncReset
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: ::ResetType::SyncReset,
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EventControl::AtPosEdge, resetSignal, std::function<void()>(),
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[&]() { builder->create<sv::PAssignOp>(destVal, srcVal); });
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return success();
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}
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@ -245,8 +245,74 @@ static void printEventList(OpAsmPrinter &p, AlwaysOp op, ArrayAttr portsAttr,
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}
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}
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//===----------------------------------------------------------------------===//
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// AlwaysFFOp
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void AlwaysFFOp::build(OpBuilder &odsBuilder, OperationState &result,
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EventControl clockEdge, Value clock,
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std::function<void()> bodyCtor) {
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result.addAttribute("clockEdge", odsBuilder.getI32IntegerAttr(
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static_cast<int32_t>(clockEdge)));
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result.addOperands(clock);
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result.addAttribute(
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"resetStyle",
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odsBuilder.getI32IntegerAttr(static_cast<int32_t>(ResetType::NoReset)));
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// Set up the body.
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Region *bodyBlk = result.addRegion();
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AlwaysFFOp::ensureTerminator(*bodyBlk, odsBuilder, result.location);
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if (bodyCtor) {
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auto oldIP = &*odsBuilder.getInsertionPoint();
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odsBuilder.setInsertionPointToStart(&*bodyBlk->begin());
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bodyCtor();
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odsBuilder.setInsertionPoint(oldIP);
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}
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// Set up the reset
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Region *resetBlk = result.addRegion();
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}
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void AlwaysFFOp::build(OpBuilder &odsBuilder, OperationState &result,
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EventControl clockEdge, Value clock,
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ResetType resetStyle, EventControl resetEdge,
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Value reset, std::function<void()> resetCtor,
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std::function<void()> bodyCtor) {
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result.addAttribute("clockEdge", odsBuilder.getI32IntegerAttr(
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static_cast<int32_t>(clockEdge)));
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result.addOperands(clock);
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result.addAttribute("resetStyle", odsBuilder.getI32IntegerAttr(
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static_cast<int32_t>(resetStyle)));
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result.addAttribute("resetEdge", odsBuilder.getI32IntegerAttr(
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static_cast<int32_t>(resetEdge)));
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result.addOperands(reset);
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// Set up the body.
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Region *bodyRegion = result.addRegion();
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if (bodyCtor) {
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AlwaysFFOp::ensureTerminator(*bodyRegion, odsBuilder, result.location);
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auto oldIP = &*odsBuilder.getInsertionPoint();
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odsBuilder.setInsertionPointToStart(&*bodyRegion->begin());
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bodyCtor();
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odsBuilder.setInsertionPoint(oldIP);
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}
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// Set up the reset.
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Region *resetRegion = result.addRegion();
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if (resetCtor) {
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AlwaysFFOp::ensureTerminator(*resetRegion, odsBuilder, result.location);
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auto oldIP = &*odsBuilder.getInsertionPoint();
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odsBuilder.setInsertionPointToStart(&*resetRegion->begin());
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resetCtor();
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odsBuilder.setInsertionPoint(oldIP);
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}
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}
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//===----------------------------------------------------------------------===//
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// InitialOp
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//===----------------------------------------------------------------------===//
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void InitialOp::build(OpBuilder &odsBuilder, OperationState &result,
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std::function<void()> bodyCtor) {
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odsBuilder.setInsertionPoint(oldIP);
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}
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}
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//===----------------------------------------------------------------------===//
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// TypeDecl operations
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//===----------------------------------------------------------------------===//
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@ -312,6 +312,7 @@ public:
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LogicalResult visitSV(IfDefOp op);
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LogicalResult visitSV(IfOp op);
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LogicalResult visitSV(AlwaysOp op);
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LogicalResult visitSV(AlwaysFFOp op);
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LogicalResult visitSV(InitialOp op);
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LogicalResult visitSV(FWriteOp op);
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LogicalResult visitSV(FatalOp op);
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return success();
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}
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LogicalResult ModuleEmitter::visitSV(AlwaysFFOp op) {
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SmallPtrSet<Operation *, 8> ops;
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ops.insert(op);
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indent() << "always_ff @(" << stringifyEventControl(op.clockEdge()) << " "
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<< emitExpressionToString(op.clock(), ops);
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if (op.resetStyle() == ResetType::AsyncReset) {
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os << " or " << stringifyEventControl(*op.resetEdge()) << " "
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<< emitExpressionToString(op.reset(), ops);
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}
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os << ')';
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// Build the comment string, leave out the signal expressions (since they
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// can be large).
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std::string comment;
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comment = "always_ff @(";
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comment += stringifyEventControl(op.clockEdge());
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if (op.resetStyle() == ResetType::AsyncReset) {
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comment += " or ";
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comment += stringifyEventControl(*op.resetEdge());
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}
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comment += ')';
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if (op.resetStyle() == ResetType::NoReset)
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emitBeginEndRegion(op.getBodyBlock(), ops, *this, comment);
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else {
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os << " begin";
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emitLocationInfoAndNewLine(ops);
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addIndent();
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indent() << "if (";
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// Negative edge async resets need to invert the reset condition. This is
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// noted in the op description.
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if (op.resetStyle() == ResetType::AsyncReset &&
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*op.resetEdge() == EventControl::AtNegEdge)
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os << "!";
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os << emitExpressionToString(op.reset(), ops) << ')';
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emitBeginEndRegion(op.getResetBlock(), ops, *this);
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indent() << "else";
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emitBeginEndRegion(op.getBodyBlock(), ops, *this);
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reduceIndent();
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indent() << "end";
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os << " // " << comment;
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os << '\n';
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}
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return success();
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}
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LogicalResult ModuleEmitter::visitSV(InitialOp op) {
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SmallPtrSet<Operation *, 8> ops;
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ops.insert(op);
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@ -479,7 +479,7 @@ module attributes {firrtl.mainModule = "Simple"} {
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%4 = firrtl.mux(%2, %3, %count) : (!firrtl.uint<1>, !firrtl.uint<2>, !firrtl.uint<2>) -> !firrtl.uint<2>
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%5 = firrtl.mux(%1, %c0_ui2, %4) : (!firrtl.uint<1>, !firrtl.uint<2>, !firrtl.uint<2>) -> !firrtl.uint<2>
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// CHECK-NEXT: sv.always posedge %clock {
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// CHECK-NEXT: sv.alwaysff posedge, %clock {
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// CHECK-NEXT: sv.passign %count, %2 : i2
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// CHECK-NEXT: }
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firrtl.connect %count, %5 : !firrtl.uint<2>, !firrtl.uint<2>
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@ -522,11 +522,11 @@ module attributes {firrtl.mainModule = "Simple"} {
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// CHECK-NEXT: sv.initial {
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// CHECK-NEXT: sv.verbatim "`INIT_RANDOM_PROLOG_"
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// CHECK-NEXT: sv.ifdef "RANDOMIZE_REG_INIT" {
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// CHECK-NEXT: %true_1 = rtl.constant(true) : i1
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// CHECK-NEXT: %9 = rtl.xor %reset, %true_1 : i1
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// CHECK-NEXT: sv.if %9 {
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// CHECK-NEXT: %10 = sv.textual_value "`RANDOM" : i32
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// CHECK-NEXT: sv.bpassign %reg, %10 : i32
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// CHECK-NEXT: %true = rtl.constant(true) : i1
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// CHECK-NEXT: %8 = rtl.xor %reset, %true : i1
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// CHECK-NEXT: sv.if %8 {
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// CHECK-NEXT: %9 = sv.textual_value "`RANDOM" : i32
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// CHECK-NEXT: sv.bpassign %reg, %9 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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@ -540,11 +540,11 @@ module attributes {firrtl.mainModule = "Simple"} {
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// CHECK-NEXT: sv.ifdef "!SYNTHESIS" {
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// CHECK-NEXT: sv.initial {
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// CHECK-NEXT: sv.ifdef "RANDOMIZE_REG_INIT" {
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// CHECK-NEXT: %true_1 = rtl.constant(true) : i1
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// CHECK-NEXT: %9 = rtl.xor %reset, %true_1 : i1
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// CHECK-NEXT: sv.if %9 {
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// CHECK-NEXT: %10 = sv.textual_value "`RANDOM" : i32
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// CHECK-NEXT: sv.bpassign %reg2, %10 : i32
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// CHECK-NEXT: %true = rtl.constant(true) : i1
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// CHECK-NEXT: %8 = rtl.xor %reset, %true : i1
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// CHECK-NEXT: sv.if %8 {
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// CHECK-NEXT: %9 = sv.textual_value "`RANDOM" : i32
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// CHECK-NEXT: sv.bpassign %reg2, %9 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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@ -565,18 +565,15 @@ module attributes {firrtl.mainModule = "Simple"} {
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%shorten = firrtl.head %sum, 32 : (!firrtl.uint<33>) -> !firrtl.uint<32>
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%5 = firrtl.mux(%3, %2, %shorten) : (!firrtl.uint<1>, !firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32>
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// CHECK-NEXT: %true = rtl.constant(true) : i1
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// CHECK-NEXT: %7 = rtl.xor %reset, %true : i1
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// CHECK-NEXT: sv.always posedge %clock, posedge %reset {
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// CHECK-NEXT: sv.if %7 {
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// CHECK-NEXT: sv.passign %reg, %6 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: sv.alwaysff posedge, %clock, asyncreset, posedge, %reset {
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// CHECK-NEXT: } {
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// CHECK-NEXT: sv.passign %reg, %6 : i32
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// CHECK-NEXT: }
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firrtl.connect %reg, %5 : !firrtl.uint<32>, !firrtl.uint<32>
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%6 = firrtl.stdIntCast %reg : (!firrtl.uint<32>) -> i32
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// CHECK-NEXT: %8 = rtl.read_inout %reg : !rtl.inout<i32>
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// CHECK-NEXT: rtl.output %8 : i32
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// CHECK-NEXT: %7 = rtl.read_inout %reg : !rtl.inout<i32>
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// CHECK-NEXT: rtl.output %7 : i32
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rtl.output %6 : i32
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}
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@ -42,6 +42,37 @@ func @test1(%arg0: i1, %arg1: i1) {
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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sv.alwaysff "posedge", %arg0 {
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sv.fwrite "Yo\n"
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}
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// CHECK-NEXT: sv.alwaysff posedge, %arg0 {
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// CHECK-NEXT: sv.fwrite "Yo\0A"
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// CHECK-NEXT: }
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sv.alwaysff "posedge", %arg0, syncreset, "posedge", %arg1 {
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sv.fwrite "Sync Reset Block\n"
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} {
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sv.fwrite "Sync Main Block\n"
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}
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// CHECK-NEXT: sv.alwaysff posedge, %arg0, syncreset, posedge, %arg1 {
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// CHECK-NEXT: sv.fwrite "Sync Reset Block\0A"
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// CHECK-NEXT: } {
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// CHECK-NEXT: sv.fwrite "Sync Main Block\0A"
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// CHECK-NEXT: }
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sv.alwaysff "posedge", %arg0, asyncreset, "negedge", %arg1 {
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sv.fwrite "Async Reset Block\n"
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} {
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sv.fwrite "Async Main Block\n"
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}
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// CHECK-NEXT: sv.alwaysff posedge, %arg0, asyncreset, negedge, %arg1 {
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// CHECK-NEXT: sv.fwrite "Async Reset Block\0A"
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// CHECK-NEXT: } {
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// CHECK-NEXT: sv.fwrite "Async Main Block\0A"
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// CHECK-NEXT: }
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// Smoke test generic syntax.
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"sv.if"(%arg0) ( {
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@ -40,6 +40,36 @@ rtl.module @M1(%clock : i1, %cond : i1, %val : i8) {
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sv.always posedge %clock, negedge %cond {
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}
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// CHECK-NEXT: always_ff @(posedge clock)
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// CHECK-NEXT: $fwrite(32'h80000002, "Yo\n");
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sv.alwaysff "posedge", %clock {
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sv.fwrite "Yo\n"
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}
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// CHECK-NEXT: always_ff @(posedge clock) begin
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// CHECK-NEXT: if (cond)
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// CHECK-NEXT: $fwrite(32'h80000002, "Sync Reset Block\n")
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// CHECK-NEXT: else
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// CHECK-NEXT: $fwrite(32'h80000002, "Sync Main Block\n");
|
||||
// CHECK-NEXT: end // always_ff @(posedge)
|
||||
sv.alwaysff "posedge", %clock, syncreset, "posedge", %cond {
|
||||
sv.fwrite "Sync Reset Block\n"
|
||||
} {
|
||||
sv.fwrite "Sync Main Block\n"
|
||||
}
|
||||
|
||||
// CHECK-NEXT: always_ff @(posedge clock or negedge cond) begin
|
||||
// CHECK-NEXT: if (!cond)
|
||||
// CHECK-NEXT: $fwrite(32'h80000002, "Async Reset Block\n");
|
||||
// CHECK-NEXT: else
|
||||
// CHECK-NEXT: $fwrite(32'h80000002, "Async Main Block\n");
|
||||
// CHECK-NEXT: end // always_ff @(posedge or negedge)
|
||||
sv.alwaysff "posedge", %clock, asyncreset, "negedge", %cond {
|
||||
sv.fwrite "Async Reset Block\n"
|
||||
} {
|
||||
sv.fwrite "Async Main Block\n"
|
||||
}
|
||||
|
||||
%c42 = rtl.constant (42 : i42) : i42
|
||||
|
||||
// CHECK-NEXT: if (cond)
|
||||
|
|
Loading…
Reference in New Issue