mirror of https://github.com/llvm/circt.git
[FIRRTL] Make emit-metadata a mlir::ModuleOp pass (#5247)
Make the `CreateSiFiveMetadata` a `mlir::ModuleOp` pass. This is required to generate `om` Dialect operations (#5224). The `om::ClassOp` must have `mlir::ModuleOp` as the parent. This PR updates the Pass infrastructure and also the lit tests.
This commit is contained in:
Prithayan Barua
GitHub
parent
6723ec62de
commit
cc5c6c84f7
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@ -169,7 +169,7 @@ def AddSeqMemPorts : Pass<"firrtl-add-seqmem-ports", "firrtl::CircuitOp"> {
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];
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}
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def CreateSiFiveMetadata : Pass<"firrtl-emit-metadata", "firrtl::CircuitOp"> {
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def CreateSiFiveMetadata : Pass<"firrtl-emit-metadata", "mlir::ModuleOp"> {
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let summary = "Emit metadata of the FIRRTL modules";
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let description = [{
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This pass handles the emission of several different kinds of metadata.
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@ -41,6 +41,7 @@ class CreateSiFiveMetadataPass
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DenseSet<Operation *> dutModuleSet;
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// The design under test module.
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FModuleOp dutMod;
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CircuitOp circuitOp;
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public:
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CreateSiFiveMetadataPass(bool _replSeqMem, StringRef _replSeqMemCircuit,
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@ -58,7 +59,6 @@ LogicalResult CreateSiFiveMetadataPass::emitMemoryMetadata() {
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if (!replSeqMem)
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return success();
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CircuitOp circuitOp = getOperation();
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// The instance graph analysis will be required to print the hierarchy names
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// of the memory.
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auto instancePathCache = InstancePathCache(getAnalysis<InstanceGraph>());
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@ -266,7 +266,6 @@ static LogicalResult removeAnnotationWithFilename(Operation *op,
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LogicalResult CreateSiFiveMetadataPass::emitRetimeModulesMetadata() {
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auto *context = &getContext();
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auto circuitOp = getOperation();
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// Get the filename, removing the annotation from the circuit.
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StringRef filename;
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@ -324,7 +323,6 @@ LogicalResult CreateSiFiveMetadataPass::emitSitestBlackboxMetadata() {
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dataTapsBlackboxClass, memTapBlackboxClass};
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auto *context = &getContext();
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auto circuitOp = getOperation();
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// Get the filenames from the annotations.
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StringRef dutFilename, testFilename;
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@ -419,7 +417,17 @@ void CreateSiFiveMetadataPass::getDependentDialects(
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}
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void CreateSiFiveMetadataPass::runOnOperation() {
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auto circuitOp = getOperation();
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auto moduleOp = getOperation();
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auto circuits = moduleOp.getOps<CircuitOp>();
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if (circuits.empty())
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return;
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auto cIter = circuits.begin();
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circuitOp = *cIter++;
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assert(cIter == circuits.end() &&
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"cannot handle more than one CircuitOp in a mlir::ModuleOp");
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auto *body = circuitOp.getBodyBlock();
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// Find the device under test and create a set of all modules underneath it.
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@ -444,6 +452,7 @@ void CreateSiFiveMetadataPass::runOnOperation() {
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// Clear pass-global state as required by MLIR pass infrastructure.
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dutMod = {};
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circuitOp = {};
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dutModuleSet.empty();
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}
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@ -125,7 +125,7 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
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pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPortsPass());
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pm.nest<firrtl::CircuitOp>().addPass(firrtl::createCreateSiFiveMetadataPass(
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pm.addPass(firrtl::createCreateSiFiveMetadataPass(
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opt.replSeqMem, opt.replSeqMemCircuit, opt.replSeqMemFile));
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pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstancesPass());
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@ -1,4 +1,4 @@
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// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-emit-metadata))' --verify-diagnostics --split-input-file %s
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// RUN: circt-opt --firrtl-emit-metadata="repl-seq-mem=true repl-seq-mem-file='dut.conf'" --verify-diagnostics -split-input-file %s
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//===----------------------------------------------------------------------===//
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// RetimeModules
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@ -1,4 +1,4 @@
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// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-emit-metadata{repl-seq-mem=true repl-seq-mem-file="dut.conf"}))' %s | FileCheck %s
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// RUN: circt-opt --firrtl-emit-metadata="repl-seq-mem=true repl-seq-mem-file='dut.conf'" -split-input-file %s | FileCheck %s
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firrtl.circuit "empty" {
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firrtl.module @empty() {
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@ -9,6 +9,8 @@ firrtl.circuit "empty" {
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// -----
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//===----------------------------------------------------------------------===//
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// RetimeModules
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//===----------------------------------------------------------------------===//
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@ -36,6 +38,8 @@ firrtl.circuit "retime0" attributes { annotations = [{
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// CHECK-SAME: output_file = #hw.output_file<"retime_modules.json", excludeFromFileList>
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// CHECK-SAME: symbols = [@retime0, @retime2]
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// -----
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//===----------------------------------------------------------------------===//
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// SitestBlackbox
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//===----------------------------------------------------------------------===//
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@ -53,6 +57,8 @@ firrtl.circuit "DUTBlackboxes" attributes { annotations = [{
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// CHECK-NOT: sv.verbatim "[]" {output_file = #hw.output_file<"", excludeFromFileList>}
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}
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// -----
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// CHECK-LABEL: firrtl.circuit "TestBlackboxes" {
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firrtl.circuit "TestBlackboxes" attributes { annotations = [{
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class = "sifive.enterprise.firrtl.SitestTestHarnessBlackBoxAnnotation",
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@ -66,6 +72,8 @@ firrtl.circuit "TestBlackboxes" attributes { annotations = [{
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// CHECK-NOT: sv.verbatim "[]" {output_file = #hw.output_file<"", excludeFromFileList>}
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}
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// -----
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// CHECK-LABEL: firrtl.circuit "BasicBlackboxes" {
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firrtl.circuit "BasicBlackboxes" attributes { annotations = [{
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class = "sifive.enterprise.firrtl.SitestBlackBoxAnnotation",
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@ -107,6 +115,8 @@ firrtl.circuit "BasicBlackboxes" attributes { annotations = [{
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// CHECK: sv.verbatim "[\0A \22DUTBlackbox1\22,\0A \22DUTBlackbox2\22\0A]" {output_file = #hw.output_file<"dut_blackboxes.json", excludeFromFileList>}
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}
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// -----
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//===----------------------------------------------------------------------===//
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// MemoryMetadata
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//===----------------------------------------------------------------------===//
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@ -117,9 +127,11 @@ firrtl.circuit "top"
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firrtl.module @top() { }
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// When there are no memories, we still need to emit the memory metadata.
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// CHECK: sv.verbatim "[]" {output_file = #hw.output_file<"metadata{{/|\\\\}}seq_mems.json", excludeFromFileList>}
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// CHECK: sv.verbatim "" {output_file = #hw.output_file<"\22dut.conf\22", excludeFromFileList>}
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// CHECK: sv.verbatim "" {output_file = #hw.output_file<"'dut.conf'", excludeFromFileList>}
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}
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// -----
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// CHECK-LABEL: firrtl.circuit "OneMemory"
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firrtl.circuit "OneMemory" {
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firrtl.module @OneMemory() {
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@ -127,9 +139,11 @@ firrtl.circuit "OneMemory" {
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}
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firrtl.memmodule @MWrite_ext(in W0_addr: !firrtl.uint<4>, in W0_en: !firrtl.uint<1>, in W0_clk: !firrtl.clock, in W0_data: !firrtl.uint<42>, in user_input: !firrtl.uint<5>) attributes {dataWidth = 42 : ui32, depth = 12 : ui64, extraPorts = [{direction = "input", name = "user_input", width = 5 : ui32}], maskBits = 1 : ui32, numReadPorts = 0 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 1 : ui32, readLatency = 1 : ui32, writeLatency = 1 : ui32}
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// CHECK: "[\0A {\0A \22module_name\22: \22MWrite_ext\22,\0A \22depth\22: 12,\0A \22width\22: 42,\0A \22masked\22: false,\0A \22read\22: 0,\0A \22write\22: 1,\0A \22readwrite\22: 0,\0A \22extra_ports\22: [\0A {\0A \22name\22: \22user_input\22,\0A \22direction\22: \22input\22,\0A \22width\22: 5\0A }\0A ],\0A \22hierarchy\22: [\0A \22OneMemory.MWrite_ext\22\0A ]\0A }\0A]"
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// CHECK: sv.verbatim "name MWrite_ext depth 12 width 42 ports write\0A" {output_file = #hw.output_file<"\22dut.conf\22"
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// CHECK: sv.verbatim "name MWrite_ext depth 12 width 42 ports write\0A" {output_file = #hw.output_file<"'dut.conf'"
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}
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// -----
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// CHECK-LABEL: firrtl.circuit "DualReadsSMem"
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firrtl.circuit "DualReadsSMem" {
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firrtl.module @DualReadsSMem() {
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@ -138,9 +152,11 @@ firrtl.circuit "DualReadsSMem" {
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firrtl.memmodule @DualReads_ext(in R0_addr: !firrtl.uint<4>, in R0_en: !firrtl.uint<1>, in R0_clk: !firrtl.clock, in R0_data: !firrtl.uint<42>, in R1_addr: !firrtl.uint<4>, in R1_en: !firrtl.uint<1>, in R1_clk: !firrtl.clock, in R1_data: !firrtl.uint<42>, in W0_addr: !firrtl.uint<4>, in W0_en: !firrtl.uint<1>, in W0_clk: !firrtl.clock, in W0_data: !firrtl.uint<42>) attributes {dataWidth = 42 : ui32, depth = 12 : ui64, extraPorts = [], maskBits = 1 : ui32, numReadPorts = 2 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 1 : ui32, readLatency = 1 : ui32, writeLatency = 1 : ui32}
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// CHECK: sv.verbatim "[\0A {\0A \22module_name\22: \22DualReads_ext\22,\0A \22depth\22: 12,\0A \22width\22: 42,\0A \22masked\22: false,\0A \22read\22: 2,\0A \22write\22: 1,\0A \22readwrite\22: 0,\0A \22extra_ports\22: [],\0A \22hierarchy\22: [\0A \22DualReadsSMem.DualReads_ext\22\0A ]\0A }\0A]"
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// CHECK: {output_file = #hw.output_file<"metadata{{/|\\\\}}seq_mems.json", excludeFromFileList>}
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// CHECK: sv.verbatim "name DualReads_ext depth 12 width 42 ports write,read,read\0A" {output_file = #hw.output_file<"\22dut.conf\22"
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// CHECK: sv.verbatim "name DualReads_ext depth 12 width 42 ports write,read,read\0A" {output_file = #hw.output_file<"'dut.conf'"
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}
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// -----
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// CHECK-LABEL: firrtl.circuit "top"
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firrtl.circuit "top" {
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firrtl.module @top() {
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@ -169,5 +185,5 @@ firrtl.circuit "top" {
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// CHECK: sv.verbatim "[\0A {\0A \22module_name\22: \22memory_ext\22,\0A \22depth\22: 16,\0A \22width\22: 8,\0A \22masked\22: false,\0A \22read\22: 1,\0A \22write\22: 0,\0A \22readwrite\22: 1,\0A \22extra_ports\22: [],\0A \22hierarchy\22: [\0A \22DUT.mem1.memory_ext\22\0A ]\0A },\0A {\0A \22module_name\22: \22dumm_ext\22,\0A \22depth\22: 20,\0A \22width\22: 5,\0A \22masked\22: false,\0A \22read\22: 1,\0A \22write\22: 1,\0A \22readwrite\22: 0,\0A \22extra_ports\22: [],\0A \22hierarchy\22: [\0A \22DUT.mem1.dumm_ext\22\0A ]\0A }\0A]"
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// CHECK-SAME: output_file = #hw.output_file<"metadata{{/|\\\\}}seq_mems.json", excludeFromFileList>
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// CHECK: sv.verbatim "name head_ext depth 20 width 5 ports write\0Aname head_0_ext depth 20 width 5 ports write\0Aname memory_ext depth 16 width 8 ports read,rw\0Aname dumm_ext depth 20 width 5 ports write,read\0A"
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// CHECK-SAME: {output_file = #hw.output_file<"\22dut.conf\22", excludeFromFileList>}
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// CHECK-SAME: {output_file = #hw.output_file<"'dut.conf'", excludeFromFileList>}
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}
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