mirror of https://github.com/llvm/circt.git
[ExtractTestCode] Use non-empty unqiue port names (#6283)
Update ETC to add non-empty and unique port names. --------- Co-authored-by: Nandor Licker <n@ndor.email>
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@ -22,8 +22,10 @@
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#include "circt/Dialect/SV/SVPasses.h"
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#include "circt/Dialect/Seq/SeqDialect.h"
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#include "circt/Dialect/Seq/SeqOps.h"
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#include "circt/Support/Namespace.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/IRMapping.h"
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#include "llvm/ADT/SetVector.h"
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#include <set>
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@ -202,12 +204,15 @@ static hw::HWModuleOp createModuleForCut(hw::HWModuleOp op,
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// Construct the ports, this is just the input Values
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SmallVector<hw::PortInfo> ports;
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{
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Namespace portNames;
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auto srcPorts = op.getInputNames();
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for (auto port : llvm::enumerate(realInputs)) {
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auto name = getNameForPort(port.value(), srcPorts);
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ports.push_back(
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{{name, port.value().getType(), hw::ModulePort::Direction::Input},
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port.index()});
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auto name = getNameForPort(port.value(), srcPorts).getValue();
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name = portNames.newName(name.empty() ? "port_" + Twine(port.index())
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: name);
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ports.push_back({{b.getStringAttr(name), port.value().getType(),
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hw::ModulePort::Direction::Input},
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port.index()});
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}
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}
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@ -552,3 +552,26 @@ module {
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hw.output
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}
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}
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// -----
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// Check that no anonymous ports are created and all the port names are unique.
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module {
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hw.module @PortName(in %clock : !seq.clock, in %in : i1) {
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%x = hw.instance "pF" @PortNameFoo(clock: %clock: !seq.clock, "": %in: i1) -> (o: i1)
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hw.output
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}
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// CHECK-LABEL: hw.module @PortNameFoo_cover
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// CHECK-SAME: (in %clock : !seq.clock, in %port_1 : i1, in %port_2 : i1)
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hw.module private @PortNameFoo(in %clock: !seq.clock, in %1: i1, out o : i1) {
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// CHECK: hw.instance "PortNameFoo_cover"
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// CHECK-SAME: @PortNameFoo_cover(clock: %clock: !seq.clock, port_1: %arg0: i1, port_2: %0: i1) -> ()
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%0 = seq.from_clock %clock
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%2 = comb.xor %1, %1 : i1
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sv.cover.concurrent posedge %0, %1 label "cover__hello1"
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sv.cover.concurrent posedge %0, %2 label "cover__hello2"
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hw.output %2 : i1
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}
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}
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