[RTL Sim] Add '--assert' to verilator compile

Previously, verilator was ignoring asserts in SystemVerilog. As a result, some
tests were passing when they should have failed.

tools/circt-rtl-sim/circt-rtl-sim.py.in

@@ -103,7 +103,7 @@ class Verilator:
         self.ldPaths = ":".join([os.path.dirname(x) for x in dpiLibs])
         return subprocess.run([self.verilator, "--cc", "--top-module",
                                self.top, "-sv", "--build", "--exe",
-                               "--Mdir", self.ObjDir] + sources)
+                               "--Mdir", self.ObjDir, "--assert"] + sources)
 
     def run(self, cycles, args):
         exe = os.path.join(self.ObjDir, "V" + self.top)