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[ExportVerilog] Remove #ifdef'd out code I inadvertantly committed, NFC.

This commit is contained in:
Chris Lattner 2021-09-17 18:24:10 -07:00
parent 3cbdf1f139
commit bb9781ce49
1 changed files with 1 additions and 19 deletions
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20
lib/Translation/ExportVerilog/ExportVerilog.cpp
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@ -3035,25 +3035,7 @@ void ModuleEmitter::emitHWModule(HWModuleOp module) {
auto moduleNameAttr = module.getNameAttr(); auto moduleNameAttr = module.getNameAttr();
verifyModuleName(module, moduleNameAttr); verifyModuleName(module, moduleNameAttr);
os << "module " << moduleNameAttr.getValue(); os << "module " << moduleNameAttr.getValue() << '(';
#if 0
// If we have any parameters, print them on their own line.
if (!module.parameters().empty()) {
os << "\n #(";
// parameters os
<< ") ";
r"
module foo
#(parameter[41 : 0] p1 = 17,
parameter [0:0] p2) (input clk);
endmodule";
}
#endif
os << '(';
if (!portInfo.empty()) if (!portInfo.empty())
emitLocationInfoAndNewLine(moduleOpSet); emitLocationInfoAndNewLine(moduleOpSet);