mirror of https://github.com/llvm/circt.git
[ExportVerilog] Fix crash when spilling LTL expr to wire (#5625)
Do not try to resolve use-before-def on LTL expressions by spilling them to a wire. LTL expressions are always emitted inline, so just leave them be in the IR and have ExportVerilog emit them as they are. Fixes #5613.
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@ -827,6 +827,10 @@ static LogicalResult legalizeHWModule(Block &block,
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return failure();
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}
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// Do not reorder LTL expressions, which are always emitted inline.
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if (isa<ltl::LTLDialect>(op.getDialect()))
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continue;
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// Name legalization should have happened in a different pass for these sv
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// elements and we don't want to change their name through re-legalization
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// (e.g. letting a temporary take the name of an unvisited wire). Adding
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@ -1083,6 +1087,10 @@ static LogicalResult legalizeHWModule(Block &block,
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SmallPtrSet<Operation *, 32> seenOperations;
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for (auto &op : llvm::make_early_inc_range(block)) {
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// Do not reorder LTL expressions, which are always emitted inline.
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if (isa<ltl::LTLDialect>(op.getDialect()))
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continue;
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// Check the users of any expressions to see if they are
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// lexically below the operation itself. If so, it is being used out
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// of order.
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@ -228,3 +228,18 @@ module attributes { circt.loweringOptions = "disallowPackedStructAssignments"} {
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hw.output %0, %0 : !T, !T
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}
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}
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// -----
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// LTL expressions that are used before being defined should not be spilled to
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// wires, where they crash the PrepareForEmission pass. They are always emitted
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// inline, so no need to restructure the IR.
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// CHECK-LABEL: hw.module @Issue5613
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hw.module @Issue5613(%a: i1, %b: i1) {
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verif.assert %2 : !ltl.sequence
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%0 = ltl.implication %2, %1 : !ltl.sequence, !ltl.property
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%1 = ltl.or %b, %3 : i1, !ltl.property
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%2 = ltl.and %b, %4 : i1, !ltl.sequence
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%3 = ltl.not %b : i1
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%4 = ltl.delay %a, 42 : i1
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hw.output
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}
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