mirror of https://github.com/llvm/circt.git
[ESI] Switch to the new parameter model.
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@ -56,6 +56,8 @@ class ESIHWBuilder : public circt::ImplicitLocOpBuilder {
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public:
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ESIHWBuilder(Operation *top);
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ArrayAttr getStageParameterList(Attribute value);
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HWModuleExternOp declareStage(Operation *symTable, Type);
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// Will be unused when CAPNP is undefined
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HWModuleExternOp declareCosimEndpoint(Operation *symTable, Type sendType,
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@ -69,7 +71,7 @@ public:
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const StringAttr dataOutValid, dataOutReady, dataOut, dataInValid,
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dataInReady, dataIn;
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const StringAttr clk, rstn;
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const Identifier width;
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const StringAttr width;
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// Various identifier strings. Keep them all here in case we rename them.
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static constexpr char dataStr[] = "data", validStr[] = "valid",
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@ -109,7 +111,7 @@ ESIHWBuilder::ESIHWBuilder(Operation *top)
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dataIn(StringAttr::get(getContext(), "DataIn")),
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clk(StringAttr::get(getContext(), "clk")),
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rstn(StringAttr::get(getContext(), "rstn")),
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width(Identifier::get("WIDTH", getContext())) {
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width(StringAttr::get(getContext(), "WIDTH")) {
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auto regions = top->getRegions();
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if (regions.size() == 0) {
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@ -170,6 +172,14 @@ StringAttr ESIHWBuilder::constructInterfaceName(ChannelPort port) {
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return constructUniqueSymbol(tableOp, proposedName);
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}
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/// Return a parameter list for the stage module with the specified value.
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ArrayAttr ESIHWBuilder::getStageParameterList(Attribute value) {
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auto type = IntegerType::get(width.getContext(), 32, IntegerType::Unsigned);
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auto widthParam =
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ParameterAttr::get(width, TypeAttr::get(type), value, width.getContext());
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return ArrayAttr::get(width.getContext(), widthParam);
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}
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/// Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module. Said
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/// module implements pipeline stage, adding 1 cycle latency. This particular
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/// implementation is double-buffered and fully pipelines the reverse-flow ready
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@ -192,9 +202,10 @@ HWModuleExternOp ESIHWBuilder::declareStage(Operation *symTable,
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{x, PortDirection::OUTPUT, dataType, 1},
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{xValid, PortDirection::OUTPUT, getI1Type(), 2},
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{xReady, PortDirection::INPUT, getI1Type(), 4}};
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stage = create<HWModuleExternOp>(
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constructUniqueSymbol(symTable, "ESI_PipelineStage"), ports,
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"ESI_PipelineStage");
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"ESI_PipelineStage", getStageParameterList({}));
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return stage;
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}
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@ -563,11 +574,8 @@ void ESIPortsPass::updateInstance(HWModuleOp mod, InstanceOp inst) {
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// -----
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// Clone the instance.
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b.setInsertionPointAfter(inst);
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DictionaryAttr parameters;
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if (inst.oldParameters().hasValue())
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parameters = inst.oldParameters().getValue();
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auto newInst = b.create<InstanceOp>(mod, inst.instanceNameAttr(), newOperands,
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parameters, inst.sym_nameAttr());
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inst.parameters(), inst.sym_nameAttr());
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// -----
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// Wrap the results back into ESI channels and connect up all the ready
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@ -801,13 +809,9 @@ void ESIPortsPass::updateInstance(HWModuleExternOp mod, InstanceOp inst) {
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}
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// Create the new instance!
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DictionaryAttr parameters;
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if (inst.oldParameters().hasValue())
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parameters = inst.oldParameters().getValue();
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InstanceOp newInst =
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instBuilder.create<InstanceOp>(mod, inst.instanceNameAttr(), newOperands,
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parameters, inst.sym_nameAttr());
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inst.parameters(), inst.sym_nameAttr());
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// Go through the old list of non-ESI result values, and replace them with the
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// new non-ESI results.
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@ -852,9 +856,10 @@ LogicalResult PipelineStageLowering::matchAndRewrite(
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Operation *symTable = stage->getParentWithTrait<OpTrait::SymbolTable>();
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auto stageModule = builder.declareStage(symTable, chPort.getInner());
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NamedAttrList stageParams;
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size_t width = circt::hw::getBitWidth(chPort.getInner());
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stageParams.set(builder.width, rewriter.getUI32IntegerAttr(width));
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ArrayAttr stageParams =
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builder.getStageParameterList(rewriter.getUI32IntegerAttr(width));
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// Unwrap the channel. The ready signal is a Value we haven't created yet, so
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// create a temp value and replace it later. Give this constant an odd-looking
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@ -872,9 +877,8 @@ LogicalResult PipelineStageLowering::matchAndRewrite(
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circt::Backedge stageReady = back.get(rewriter.getI1Type());
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Value operands[] = {stage.clk(), stage.rstn(), unwrap.rawOutput(),
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unwrap.valid(), stageReady};
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auto stageInst = rewriter.create<InstanceOp>(
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loc, stageModule, pipeStageName, operands,
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stageParams.getDictionary(rewriter.getContext()), StringAttr());
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auto stageInst = rewriter.create<InstanceOp>(loc, stageModule, pipeStageName,
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operands, stageParams);
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auto stageInstResults = stageInst.getResults();
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// Set a_ready (from the unwrap) back edge correctly to its output from stage.
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