[ExportVerilog] Allow ArraySlices to be emitted inline

New ArraySlice Verilog syntax only uses the idx operator once.

lib/Translation/ExportVerilog/ExportVerilog.cpp

@@ -1612,10 +1612,6 @@ static bool isExpressionUnableToInline(Operation *op) {
           !isOkToBitSelectFrom(op->getResult(0)))
         return true;
     }
-    // ArraySliceOp uses its operand twice, so we want to assign it first then
-    // use that variable in the ArraySliceOp expression.
-    if (isa<ArraySliceOp>(user))
-      return true;
   }
   return false;
 }
@@ -1980,4 +1976,4 @@ void circt::registerToVerilogTranslation() {
       "emit-verilog", exportVerilog, [](DialectRegistry &registry) {
         registry.insert<RTLDialect, SVDialect>();
       });
-}
+}