mirror of https://github.com/llvm/circt.git
[FIRRTL] Add a memory flattening pass (#2967)
Create a new pass to flatten the aggregate memory instead of doing it in LowerTypes. This commit removes the logic from LowerTypes and moves it into a new pass that should run before LowerTypes.
This commit is contained in:
Prithayan Barua
GitHub
parent
b9c82fa7bf
commit
ac5036c3b3
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@ -29,8 +29,7 @@ createLowerFIRRTLAnnotationsPass(bool ignoreUnhandledAnnotations = false,
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bool ignoreClasslessAnnotations = false);
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std::unique_ptr<mlir::Pass>
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createLowerFIRRTLTypesPass(bool replSeqMem = false,
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bool preserveAggregate = false,
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createLowerFIRRTLTypesPass(bool preserveAggregate = false,
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bool preservePublicTypes = true);
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std::unique_ptr<mlir::Pass> createLowerBundleVectorTypesPass();
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@ -46,6 +45,8 @@ std::unique_ptr<mlir::Pass> createInlinerPass();
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std::unique_ptr<mlir::Pass> createInferReadWritePass();
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std::unique_ptr<mlir::Pass> createLowerMemoryPass();
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std::unique_ptr<mlir::Pass> createBlackBoxMemoryPass();
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std::unique_ptr<mlir::Pass>
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@ -409,4 +409,12 @@ def InferReadWrite : Pass<"firrtl-infer-rw", "firrtl::FModuleOp"> {
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let constructor = "circt::firrtl::createInferReadWritePass()";
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}
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def LowerMemory : Pass<"firrtl-lower-memory", "firrtl::FModuleOp"> {
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let summary = "Flatten aggregate memory data to a UInt";
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let description = [{
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This pass flattens aggregate memory data field into a UInt, and
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inserts the appropriate logic to access the data.
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}];
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let constructor = "circt::firrtl::createLowerMemoryPass()";
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}
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#endif // CIRCT_DIALECT_FIRRTL_PASSES_TD
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@ -15,6 +15,7 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms
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InferWidths.cpp
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LowerAnnotations.cpp
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LowerCHIRRTL.cpp
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LowerMemory.cpp
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LowerTypes.cpp
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MergeConnections.cpp
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ModuleInliner.cpp
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@ -0,0 +1,230 @@
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//===- LowerMemory.cpp - Lower Memory Pass -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the LowerMemory pass.
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//
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//===----------------------------------------------------------------------===//
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#include "PassDetails.h"
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#include "circt/Dialect/FIRRTL/FIRRTLAnnotations.h"
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#include "circt/Dialect/FIRRTL/FIRRTLOps.h"
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#include "circt/Dialect/FIRRTL/FIRRTLTypes.h"
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#include "circt/Dialect/FIRRTL/Namespace.h"
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#include "circt/Dialect/FIRRTL/Passes.h"
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#include "mlir/IR/ImplicitLocOpBuilder.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "lower-memory"
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using namespace circt;
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using namespace firrtl;
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namespace {
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struct LowerMemoryPass : public LowerMemoryBase<LowerMemoryPass> {
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/// This pass flattens the aggregate data of memory into a UInt, and inserts
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/// appropriate bitcasts to access the data.
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void runOnOperation() override {
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LLVM_DEBUG(llvm::dbgs() << "\n Running lower memory on module:"
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<< getOperation().getName());
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ModuleNamespace modNamespace(getOperation());
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SmallVector<Operation *> opsToErase;
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auto hasSubAnno = [&](MemOp op) -> bool {
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for (size_t portIdx = 0, e = op.getNumResults(); portIdx < e; ++portIdx)
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for (auto attr : op.getPortAnnotation(portIdx))
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if (auto subAnno = attr.dyn_cast<SubAnnotationAttr>())
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return true;
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return false;
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};
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getOperation().getBody()->walk([&](MemOp memOp) {
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LLVM_DEBUG(llvm::dbgs() << "\n Memory:" << memOp);
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// The vector of leaf elements type after flattening the data.
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SmallVector<IntType> flatMemType;
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// MaskGranularity : how many bits each mask bit controls.
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size_t maskGran = 1;
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// Total mask bitwidth after flattening.
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uint32_t totalmaskWidths = 0;
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// How many mask bits each field type requires.
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SmallVector<unsigned> maskWidths;
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// If subannotations present on aggregate fields, we cannot flatten the
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// memory. It must be split into one memory per aggregate field.
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// Do not overwrite the pass flag!
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if (hasSubAnno(memOp) || !flattenType(memOp.getDataType(), flatMemType))
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return;
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SmallVector<Operation *, 8> flatData;
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SmallVector<int32_t> memWidths;
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// Get the width of individual aggregate leaf elements.
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for (auto f : flatMemType) {
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LLVM_DEBUG(llvm::dbgs() << "\n field type:" << f);
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memWidths.push_back(f.getWidth().getValue());
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}
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maskGran = memWidths[0];
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size_t memFlatWidth = 0;
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// Compute the GCD of all data bitwidths.
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for (auto w : memWidths) {
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memFlatWidth += w;
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maskGran = llvm::GreatestCommonDivisor64(maskGran, w);
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}
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for (auto w : memWidths) {
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// How many mask bits required for each flattened field.
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auto mWidth = w / maskGran;
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maskWidths.push_back(mWidth);
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totalmaskWidths += mWidth;
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}
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// Now create a new memory of type flattened data.
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// ----------------------------------------------
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SmallVector<Type, 8> ports;
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SmallVector<Attribute, 8> portNames;
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auto *context = memOp.getContext();
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ImplicitLocOpBuilder builder(memOp.getLoc(), memOp);
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// Create a new memoty data type of unsigned and computed width.
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auto flatType = UIntType::get(context, memFlatWidth);
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auto opPorts = memOp.getPorts();
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for (size_t portIdx = 0, e = opPorts.size(); portIdx < e; ++portIdx) {
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auto port = opPorts[portIdx];
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ports.push_back(MemOp::getTypeForPort(memOp.depth(), flatType,
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port.second, totalmaskWidths));
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portNames.push_back(port.first);
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}
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auto flatMem = builder.create<MemOp>(
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ports, memOp.readLatency(), memOp.writeLatency(), memOp.depth(),
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memOp.ruw(), builder.getArrayAttr(portNames), memOp.nameAttr(),
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memOp.annotations(), memOp.portAnnotations(), memOp.inner_symAttr(),
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memOp.groupIDAttr());
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// Hook up the new memory to the wires the old memory was replaced with.
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for (size_t index = 0, rend = memOp.getNumResults(); index < rend;
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++index) {
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auto result = memOp.getResult(index);
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auto wire = builder.create<WireOp>(
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result.getType(),
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(memOp.name() + "_" + memOp.getPortName(index).getValue()).str());
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result.replaceAllUsesWith(wire.getResult());
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result = wire;
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auto newResult = flatMem.getResult(index);
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auto rType = result.getType().cast<BundleType>();
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for (size_t fieldIndex = 0, fend = rType.getNumElements();
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fieldIndex != fend; ++fieldIndex) {
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auto name = rType.getElement(fieldIndex).name.getValue();
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auto oldField = builder.create<SubfieldOp>(result, fieldIndex);
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Value newField = builder.create<SubfieldOp>(newResult, fieldIndex);
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// data and mask depend on the memory type which was split. They can
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// also go both directions, depending on the port direction.
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if (!(name == "data" || name == "mask" || name == "wdata" ||
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name == "wmask" || name == "rdata")) {
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mkConnect(&builder, newField, oldField);
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continue;
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}
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Value realOldField = oldField;
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if (rType.getElement(fieldIndex).isFlip) {
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// Cast the memory read data from flat type to aggregate.
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newField = builder.createOrFold<BitCastOp>(
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oldField.getType().cast<FIRRTLType>(), newField);
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// Write the aggregate read data.
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mkConnect(&builder, realOldField, newField);
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} else {
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// Cast the input aggregate write data to flat type.
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// Cast the input aggregate write data to flat type.
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auto newFieldType = newField.getType().cast<FIRRTLType>();
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auto oldFieldBitWidth = getBitWidth(oldField.getType());
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// Following condition is true, if a data field is 0 bits. Then
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// newFieldType is of smaller bits than old.
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if (getBitWidth(newFieldType) != oldFieldBitWidth.getValue())
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newFieldType =
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UIntType::get(context, oldFieldBitWidth.getValue());
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realOldField = builder.create<BitCastOp>(newFieldType, oldField);
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// Mask bits require special handling, since some of the mask bits
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// need to be repeated, direct bitcasting wouldn't work. Depending
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// on the mask granularity, some mask bits will be repeated.
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if ((name == "mask" || name == "wmask") &&
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(maskWidths.size() != totalmaskWidths)) {
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Value catMasks;
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for (auto m : llvm::enumerate(maskWidths)) {
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// Get the mask bit.
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auto mBit = builder.createOrFold<BitsPrimOp>(
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realOldField, m.index(), m.index());
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// Check how many times the mask bit needs to be prepend.
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for (size_t repeat = 0; repeat < m.value(); repeat++)
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if ((m.index() == 0 && repeat == 0) || !catMasks)
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catMasks = mBit;
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else
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catMasks = builder.createOrFold<CatPrimOp>(mBit, catMasks);
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}
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realOldField = catMasks;
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}
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// Now set the mask or write data.
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// Ensure that the types match.
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mkConnect(&builder, newField,
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builder.createOrFold<BitCastOp>(
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newField.getType().cast<FIRRTLType>(), realOldField));
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}
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}
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}
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memOp.erase();
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return;
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});
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}
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private:
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// Convert an aggregate type into a flat list of fields.
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// This is used to flatten the aggregate memory datatype.
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// Recursively populate the results with each ground type field.
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static bool flattenType(FIRRTLType type, SmallVectorImpl<IntType> &results) {
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std::function<bool(FIRRTLType)> flatten = [&](FIRRTLType type) -> bool {
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return TypeSwitch<FIRRTLType, bool>(type)
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.Case<BundleType>([&](auto bundle) {
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for (auto &elt : bundle)
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if (!flatten(elt.type))
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return false;
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return true;
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})
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.Case<FVectorType>([&](auto vector) {
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for (size_t i = 0, e = vector.getNumElements(); i != e; ++i)
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if (!flatten(vector.getElementType()))
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return false;
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return true;
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})
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.Case<IntType>([&](auto iType) {
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results.push_back({iType});
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return iType.getWidth().hasValue();
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})
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.Default([&](auto) { return false; });
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};
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if (flatten(type))
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return true;
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return false;
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}
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Value getSubWhatever(ImplicitLocOpBuilder *builder, Value val, size_t index) {
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if (BundleType bundle = val.getType().dyn_cast<BundleType>())
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return builder->create<SubfieldOp>(val, index);
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if (FVectorType fvector = val.getType().dyn_cast<FVectorType>())
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return builder->create<SubindexOp>(val, index);
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llvm_unreachable("Unknown aggregate type");
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return nullptr;
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}
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void mkConnect(ImplicitLocOpBuilder *builder, Value dst, Value src) {
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auto dstType = dst.getType().cast<FIRRTLType>();
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auto srcType = src.getType().cast<FIRRTLType>();
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if (srcType == dstType)
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builder->create<StrictConnectOp>(dst, src);
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else
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builder->create<ConnectOp>(dst, src);
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}
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};
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} // end anonymous namespace
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std::unique_ptr<mlir::Pass> circt::firrtl::createLowerMemoryPass() {
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return std::make_unique<LowerMemoryPass>();
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}
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@ -304,11 +304,10 @@ struct AttrCache {
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// not.
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struct TypeLoweringVisitor : public FIRRTLVisitor<TypeLoweringVisitor, bool> {
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TypeLoweringVisitor(MLIRContext *context, bool flattenAggregateMemData,
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bool preserveAggregate, bool preservePublicTypes,
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SymbolTable &symTbl, const AttrCache &cache)
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: context(context), flattenAggregateMemData(flattenAggregateMemData),
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preserveAggregate(preserveAggregate),
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TypeLoweringVisitor(MLIRContext *context, bool preserveAggregate,
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bool preservePublicTypes, SymbolTable &symTbl,
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const AttrCache &cache)
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: context(context), preserveAggregate(preserveAggregate),
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preservePublicTypes(preservePublicTypes), symTbl(symTbl), cache(cache) {
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}
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using FIRRTLVisitor<TypeLoweringVisitor, bool>::visitDecl;
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@ -376,9 +375,6 @@ private:
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}
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MLIRContext *context;
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/// Create a single memory from an aggregate type (instead of one per field)
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/// if this flag is enabled.
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bool flattenAggregateMemData;
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/// Not to lower passive aggregate types as much as possible if this flag is
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/// enabled.
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@ -932,35 +928,6 @@ bool TypeLoweringVisitor::visitStmt(WhenOp op) {
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return false; // don't delete the when!
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}
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// Convert an aggregate type into a flat list of fields.
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// This is used to flatten the aggregate memory datatype.
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// Recursively populate the results with each ground type field.
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static bool flattenType(FIRRTLType type, SmallVectorImpl<IntType> &results) {
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std::function<bool(FIRRTLType)> flatten = [&](FIRRTLType type) -> bool {
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return TypeSwitch<FIRRTLType, bool>(type)
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.Case<BundleType>([&](auto bundle) {
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for (auto &elt : bundle)
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if (!flatten(elt.type))
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return false;
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return true;
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})
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.Case<FVectorType>([&](auto vector) {
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for (size_t i = 0, e = vector.getNumElements(); i != e; ++i)
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if (!flatten(vector.getElementType()))
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return false;
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return true;
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})
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.Case<IntType>([&](auto iType) {
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results.push_back({iType});
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return iType.getWidth().hasValue();
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})
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.Default([&](auto) { return false; });
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};
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if (flatten(type))
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return true;
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return false;
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}
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/// Lower memory operations. A new memory is created for every leaf
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/// element in a memory's data type.
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bool TypeLoweringVisitor::visitDecl(MemOp op) {
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@ -983,78 +950,13 @@ bool TypeLoweringVisitor::visitDecl(MemOp op) {
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oldPorts.push_back(wire);
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result.replaceAllUsesWith(wire.getResult());
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}
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// The vector of leaf elements type after flattening the data.
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SmallVector<IntType> flatMemType;
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// MaskGranularity : how many bits each mask bit controls.
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size_t maskGran = 1;
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// Total mask bitwidth after flattening.
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uint32_t totalmaskWidths = 0;
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// How many mask bits each field type requires.
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SmallVector<unsigned> maskWidths;
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auto hasSubAnno = [&]() -> bool {
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for (size_t portIdx = 0, e = op.getNumResults(); portIdx < e; ++portIdx)
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for (auto attr : op.getPortAnnotation(portIdx)) {
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if (auto subAnno = attr.dyn_cast<SubAnnotationAttr>())
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return true;
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}
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return false;
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};
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// If subannotations present on aggregate fields, we cannot flatten the
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// memory. It must be split into one memory per aggregate field.
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// Do not overwrite the pass flag!
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auto localFlattenAggregateMemData = flattenAggregateMemData;
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if (localFlattenAggregateMemData)
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if (hasSubAnno() || !flattenType(op.getDataType(), flatMemType))
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localFlattenAggregateMemData = false;
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if (localFlattenAggregateMemData) {
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SmallVector<Operation *, 8> flatData;
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SmallVector<int32_t> memWidths;
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// Get the width of individual aggregate leaf elements.
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for (auto f : flatMemType)
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memWidths.push_back(f.getWidth().getValue());
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maskGran = memWidths[0];
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size_t memFlatWidth = 0;
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// Compute the GCD of all data bitwidths.
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for (auto w : memWidths) {
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memFlatWidth += w;
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maskGran = llvm::GreatestCommonDivisor64(maskGran, w);
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}
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for (auto w : memWidths) {
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// How many mask bits required for each flattened field.
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auto mWidth = w / maskGran;
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maskWidths.push_back(mWidth);
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totalmaskWidths += mWidth;
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}
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// Now create a new memory of type flattened data.
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// ----------------------------------------------
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SmallVector<Type, 8> ports;
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SmallVector<Attribute, 8> portNames;
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// Create a new memoty data type of unsigned and computed width.
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auto flatType = UIntType::get(context, memFlatWidth);
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auto opPorts = op.getPorts();
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for (size_t portIdx = 0, e = opPorts.size(); portIdx < e; ++portIdx) {
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auto port = opPorts[portIdx];
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ports.push_back(MemOp::getTypeForPort(op.depth(), flatType, port.second,
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totalmaskWidths));
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portNames.push_back(port.first);
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}
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auto flatMem = builder->create<MemOp>(
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ports, op.readLatency(), op.writeLatency(), op.depth(), op.ruw(),
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portNames, op.name(), op.annotations().getValue(),
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op.portAnnotations().getValue(), op.inner_symAttr());
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// Done creating the memory.
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// ----------------------------------------------
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newMemories.push_back(flatMem);
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} else {
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// Memory for each field
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for (auto field : fields)
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newMemories.push_back(cloneMemWithNewType(builder, op, field));
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}
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// Hook up the new memories to the wires the old memory was replaced with.
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for (size_t index = 0, rend = op.getNumResults(); index < rend; ++index) {
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auto result = oldPorts[index];
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@ -1067,55 +969,6 @@ bool TypeLoweringVisitor::visitDecl(MemOp op) {
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// go both directions, depending on the port direction.
|
||||
if (name == "data" || name == "mask" || name == "wdata" ||
|
||||
name == "wmask" || name == "rdata") {
|
||||
if (localFlattenAggregateMemData) {
|
||||
// If memory was flattened instead of one memory per aggregate field.
|
||||
Value newField =
|
||||
getSubWhatever(newMemories[0].getResult(index), fieldIndex);
|
||||
Value realOldField = oldField;
|
||||
if (rType.getElement(fieldIndex).isFlip) {
|
||||
// Cast the memory read data from flat type to aggregate.
|
||||
newField = builder->createOrFold<BitCastOp>(
|
||||
oldField.getType().cast<FIRRTLType>(), newField);
|
||||
// Write the aggregate read data.
|
||||
mkConnect(builder, realOldField, newField);
|
||||
} else {
|
||||
// Cast the input aggregate write data to flat type.
|
||||
auto newFieldType = newField.getType().cast<FIRRTLType>();
|
||||
auto oldFieldBitWidth = getBitWidth(oldField.getType());
|
||||
// Following condition is true, if a data field is 0 bits. Then
|
||||
// newFieldType is of smaller bits than old.
|
||||
if (getBitWidth(newFieldType) != oldFieldBitWidth.getValue())
|
||||
newFieldType =
|
||||
UIntType::get(context, oldFieldBitWidth.getValue());
|
||||
realOldField = builder->create<BitCastOp>(newFieldType, oldField);
|
||||
// Mask bits require special handling, since some of the mask bits
|
||||
// need to be repeated, direct bitcasting wouldn't work. Depending
|
||||
// on the mask granularity, some mask bits will be repeated.
|
||||
// This also handles the case, when some of the data fields are 0
|
||||
// bit, then the mask bits for zero bit data fields must be ignored.
|
||||
if ((name == "mask" || name == "wmask") &&
|
||||
(maskWidths.size() != totalmaskWidths)) {
|
||||
Value catMasks;
|
||||
for (auto m : llvm::enumerate(maskWidths)) {
|
||||
// Get the mask bit.
|
||||
auto mBit = builder->createOrFold<BitsPrimOp>(
|
||||
realOldField, m.index(), m.index());
|
||||
// Check how many times the mask bit needs to be prepend.
|
||||
for (size_t repeat = 0; repeat < m.value(); repeat++)
|
||||
if ((m.index() == 0 && repeat == 0) || !catMasks)
|
||||
catMasks = mBit;
|
||||
else
|
||||
catMasks = builder->createOrFold<CatPrimOp>(mBit, catMasks);
|
||||
}
|
||||
realOldField = catMasks;
|
||||
}
|
||||
// Now set the mask or write data.
|
||||
// Ensure that the types match.
|
||||
mkConnect(builder, newField,
|
||||
builder->createOrFold<BitCastOp>(
|
||||
newField.getType().cast<FIRRTLType>(), realOldField));
|
||||
}
|
||||
} else {
|
||||
for (auto field : fields) {
|
||||
auto realOldField = getSubWhatever(oldField, field.index);
|
||||
auto newField = getSubWhatever(
|
||||
|
|
@ -1124,7 +977,6 @@ bool TypeLoweringVisitor::visitDecl(MemOp op) {
|
|||
std::swap(realOldField, newField);
|
||||
mkConnect(builder, newField, realOldField);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (auto mem : newMemories) {
|
||||
auto newField =
|
||||
|
|
@ -1530,9 +1382,7 @@ bool TypeLoweringVisitor::visitExpr(MultibitMuxOp op) {
|
|||
|
||||
namespace {
|
||||
struct LowerTypesPass : public LowerFIRRTLTypesBase<LowerTypesPass> {
|
||||
LowerTypesPass(bool flattenAggregateMemDataFlag, bool preserveAggregateFlag,
|
||||
bool preservePublicTypesFlag) {
|
||||
flattenAggregateMemData = flattenAggregateMemDataFlag;
|
||||
LowerTypesPass(bool preserveAggregateFlag, bool preservePublicTypesFlag) {
|
||||
preserveAggregate = preserveAggregateFlag;
|
||||
preservePublicTypes = preservePublicTypesFlag;
|
||||
}
|
||||
|
|
@ -1567,9 +1417,8 @@ void LowerTypesPass::runOnOperation() {
|
|||
std::mutex nlaAppendLock;
|
||||
// This lambda, executes in parallel for each Op within the circt.
|
||||
auto lowerModules = [&](FModuleLike op) -> void {
|
||||
auto tl = TypeLoweringVisitor(&getContext(), flattenAggregateMemData,
|
||||
preserveAggregate, preservePublicTypes,
|
||||
symTbl, cache);
|
||||
auto tl = TypeLoweringVisitor(&getContext(), preserveAggregate,
|
||||
preservePublicTypes, symTbl, cache);
|
||||
tl.lowerModule(op);
|
||||
|
||||
std::lock_guard<std::mutex> lg(nlaAppendLock);
|
||||
|
|
@ -1723,9 +1572,10 @@ void LowerTypesPass::runOnOperation() {
|
|||
}
|
||||
|
||||
/// This is the pass constructor.
|
||||
std::unique_ptr<mlir::Pass> circt::firrtl::createLowerFIRRTLTypesPass(
|
||||
bool replSeqMem, bool preserveAggregate, bool preservePublicTypes) {
|
||||
std::unique_ptr<mlir::Pass>
|
||||
circt::firrtl::createLowerFIRRTLTypesPass(bool preserveAggregate,
|
||||
bool preservePublicTypes) {
|
||||
|
||||
return std::make_unique<LowerTypesPass>(replSeqMem, preserveAggregate,
|
||||
return std::make_unique<LowerTypesPass>(preserveAggregate,
|
||||
preservePublicTypes);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,150 @@
|
|||
// RUN: circt-opt -pass-pipeline='firrtl.circuit(firrtl.module(firrtl-lower-memory))' %s | FileCheck %s
|
||||
|
||||
|
||||
firrtl.circuit "Mem" {
|
||||
firrtl.module public @Mem(in %clock: !firrtl.clock, in %rAddr: !firrtl.uint<4>, in %rEn: !firrtl.uint<1>, out %rData: !firrtl.bundle<a: uint<8>, b: uint<8>>, in %wAddr: !firrtl.uint<4>, in %wEn: !firrtl.uint<1>, in %wMask: !firrtl.bundle<a: uint<1>, b: uint<1>>, in %wData: !firrtl.bundle<a: uint<8>, b: uint<8>>) {
|
||||
%memory_r, %memory_w = firrtl.mem Undefined {depth = 16 : i64, name = "memory", portNames = ["r", "w"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>, !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>
|
||||
%0 = firrtl.subfield %memory_r(2) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.clock
|
||||
firrtl.strictconnect %0, %clock : !firrtl.clock
|
||||
%1 = firrtl.subfield %memory_r(1) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.uint<1>
|
||||
firrtl.strictconnect %1, %rEn : !firrtl.uint<1>
|
||||
%2 = firrtl.subfield %memory_r(0) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.uint<4>
|
||||
firrtl.strictconnect %2, %rAddr : !firrtl.uint<4>
|
||||
%3 = firrtl.subfield %memory_r(3) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
firrtl.strictconnect %rData, %3 : !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
%4 = firrtl.subfield %memory_w(2) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.clock
|
||||
firrtl.strictconnect %4, %clock : !firrtl.clock
|
||||
%5 = firrtl.subfield %memory_w(1) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<1>
|
||||
firrtl.strictconnect %5, %wEn : !firrtl.uint<1>
|
||||
%6 = firrtl.subfield %memory_w(0) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<4>
|
||||
firrtl.strictconnect %6, %wAddr : !firrtl.uint<4>
|
||||
%7 = firrtl.subfield %memory_w(4) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
firrtl.strictconnect %7, %wMask : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
%8 = firrtl.subfield %memory_w(3) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
firrtl.strictconnect %8, %wData : !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
// ---------------------------------------------------------------------------------
|
||||
// After flattenning the memory data
|
||||
// CHECK: %[[memory_r:.+]], %[[memory_w:.+]] = firrtl.mem Undefined {depth = 16 : i64, name = "memory", portNames = ["r", "w"], readLatency = 0 : i32, writeLatency = 1 : i32}
|
||||
// CHECK-SAME: !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<16>>, !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<16>, mask: uint<2>>
|
||||
// CHECK: %[[memory_r_0:.+]] = firrtl.wire {name = "memory_r"} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>
|
||||
// CHECK: %[[v0:.+]] = firrtl.subfield %[[memory_r]](0)
|
||||
// CHECK: firrtl.strictconnect %[[v0]], %[[memory_r_addr:.+]] :
|
||||
// CHECK: %[[v1:.+]] = firrtl.subfield %[[memory_r]](1)
|
||||
// CHECK: firrtl.strictconnect %[[v1]], %[[memory_r_en:.+]] :
|
||||
// CHECK: %[[v2:.+]] = firrtl.subfield %[[memory_r]](2)
|
||||
// CHECK: firrtl.strictconnect %[[v2]], %[[memory_r_clk:.+]] :
|
||||
// CHECK: %[[v3:.+]] = firrtl.subfield %[[memory_r]](3)
|
||||
//
|
||||
// ---------------------------------------------------------------------------------
|
||||
// Read ports
|
||||
// CHECK: %[[v4:.+]] = firrtl.bitcast %[[v3]] : (!firrtl.uint<16>) -> !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
// CHECK: firrtl.strictconnect %[[memory_r_data:.+]], %[[v4]] :
|
||||
// --------------------------------------------------------------------------------
|
||||
// Write Ports
|
||||
// CHECK: %[[memory_w_1:.+]] = firrtl.wire {name = "memory_w"} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>
|
||||
// CHECK: %[[v9:.+]] = firrtl.subfield %[[memory_w]](3)
|
||||
// CHECK: %[[v17:.+]] = firrtl.bitcast %[[v15:.+]] : (!firrtl.bundle<a: uint<8>, b: uint<8>>) -> !firrtl.uint<16>
|
||||
// CHECK: firrtl.strictconnect %[[v9]], %[[v17]]
|
||||
//
|
||||
// --------------------------------------------------------------------------------
|
||||
// Mask Ports
|
||||
// CHECK: %[[v11:.+]] = firrtl.subfield %[[memory_w]](4)
|
||||
// CHECK: %[[v12:.+]] = firrtl.bitcast %[[v18:.+]] : (!firrtl.bundle<a: uint<1>, b: uint<1>>) -> !firrtl.uint<2>
|
||||
// CHECK: firrtl.strictconnect %[[v11]], %[[v12]]
|
||||
// --------------------------------------------------------------------------------
|
||||
// Connections to module ports
|
||||
// CHECK: %[[v21:.+]] = firrtl.subfield %[[memory_r_0]](2) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.clock
|
||||
// CHECK: firrtl.strictconnect %[[v21]], %clock :
|
||||
// CHECK: %[[v22:.+]] = firrtl.subfield %[[memory_r_0]](1) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.uint<1>
|
||||
// CHECK: firrtl.strictconnect %[[v22]], %rEn : !firrtl.uint<1>
|
||||
// CHECK: %[[v23:.+]] = firrtl.subfield %[[memory_r_0]](0) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.uint<4>
|
||||
// CHECK: firrtl.strictconnect %[[v23]], %rAddr : !firrtl.uint<4>
|
||||
// CHECK: %[[v24:.+]] = firrtl.subfield %[[memory_r_0]](3) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>) -> !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
// CHECK: firrtl.strictconnect %rData, %[[v24]] : !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
// CHECK: %[[v25:.+]] = firrtl.subfield %[[memory_w_1]](2) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.clock
|
||||
// CHECK: firrtl.strictconnect %[[v25]], %clock : !firrtl.clock
|
||||
// CHECK: %[[v26:.+]] = firrtl.subfield %[[memory_w_1]](1) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<1>
|
||||
// CHECK: firrtl.strictconnect %[[v26]], %wEn : !firrtl.uint<1>
|
||||
// CHECK: %[[v27:.+]] = firrtl.subfield %[[memory_w_1]](0) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<4>
|
||||
// CHECK: firrtl.strictconnect %[[v27]], %wAddr : !firrtl.uint<4>
|
||||
// CHECK: %[[v28:.+]] = firrtl.subfield %[[memory_w_1]](4) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: firrtl.strictconnect %[[v28]], %wMask : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: %[[v29:.+]] = firrtl.subfield %[[memory_w_1]](3) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: bundle<a: uint<8>, b: uint<8>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
// CHECK: firrtl.strictconnect %[[v29]], %wData : !firrtl.bundle<a: uint<8>, b: uint<8>>
|
||||
}
|
||||
|
||||
firrtl.module @MemoryRWSplit(in %clock: !firrtl.clock, in %rwEn: !firrtl.uint<1>, in %rwMode: !firrtl.uint<1>, in %rwAddr: !firrtl.uint<4>, in %rwMask: !firrtl.bundle<a: uint<1>, b: uint<1>>, in %rwDataIn: !firrtl.bundle<a: uint<8>, b: uint<9>>, out %rwDataOut: !firrtl.bundle<a: uint<8>, b: uint<9>>) {
|
||||
%memory_rw = firrtl.mem Undefined {depth = 16 : i64, groupID = 1 : ui32, name = "memory", portNames = ["rw"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>
|
||||
// CHECK: %memory_rw = firrtl.mem Undefined {depth = 16 : i64, groupID = 1 : ui32, name = "memory", portNames = ["rw"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: uint<17>, wmode: uint<1>, wdata: uint<17>, wmask: uint<17>>
|
||||
// CHECK: %[[memory_rw_0:.+]] = firrtl.wire {name = "memory_rw"} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>
|
||||
%0 = firrtl.subfield %memory_rw(3) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<8>, b: uint<9>>
|
||||
%1 = firrtl.subfield %memory_rw(5) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<8>, b: uint<9>>
|
||||
%2 = firrtl.subfield %memory_rw(6) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
%3 = firrtl.subfield %memory_rw(4) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<1>
|
||||
%4 = firrtl.subfield %memory_rw(0) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<4>
|
||||
%5 = firrtl.subfield %memory_rw(1) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.uint<1>
|
||||
%6 = firrtl.subfield %memory_rw(2) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: bundle<a: uint<8>, b: uint<9>>, wmode: uint<1>, wdata: bundle<a: uint<8>, b: uint<9>>, wmask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.clock
|
||||
firrtl.connect %6, %clock : !firrtl.clock, !firrtl.clock
|
||||
firrtl.connect %5, %rwEn : !firrtl.uint<1>, !firrtl.uint<1>
|
||||
firrtl.connect %4, %rwAddr : !firrtl.uint<4>, !firrtl.uint<4>
|
||||
firrtl.connect %3, %rwMode : !firrtl.uint<1>, !firrtl.uint<1>
|
||||
firrtl.connect %2, %rwMask : !firrtl.bundle<a: uint<1>, b: uint<1>>, !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
firrtl.connect %1, %rwDataIn : !firrtl.bundle<a: uint<8>, b: uint<9>>, !firrtl.bundle<a: uint<8>, b: uint<9>>
|
||||
firrtl.connect %rwDataOut, %0 : !firrtl.bundle<a: uint<8>, b: uint<9>>, !firrtl.bundle<a: uint<8>, b: uint<9>>
|
||||
// CHECK: %[[v6:.+]] = firrtl.subfield %[[memory_rw_0]](3) :
|
||||
// CHECK: %[[v7:.+]] = firrtl.subfield %memory_rw(3) :
|
||||
// CHECK: %[[v8:.+]] = firrtl.bitcast %[[v7]] :
|
||||
// CHECK: firrtl.strictconnect %[[v6]], %[[v8]] :
|
||||
// CHECK: %[[v9:.+]] = firrtl.subfield %[[memory_rw_0]](4) :
|
||||
// CHECK: %[[v10:.+]] = firrtl.subfield %memory_rw(4) :
|
||||
// CHECK: firrtl.strictconnect %[[v10]], %[[v9]] : !firrtl.uint<1>
|
||||
// CHECK: %[[v11:.+]] = firrtl.subfield %[[memory_rw_0]](5) :
|
||||
// CHECK: %[[v12:.+]] = firrtl.subfield %memory_rw(5) :
|
||||
// CHECK: %[[v13:.+]] = firrtl.bitcast %[[v11]] : (!firrtl.bundle<a: uint<8>, b: uint<9>>) -> !firrtl.uint<17>
|
||||
// CHECK: firrtl.strictconnect %[[v12]], %[[v13]] :
|
||||
// CHECK: %[[v14:.+]] = firrtl.subfield %[[memory_rw_0]](6) :
|
||||
// CHECK: %[[v15:.+]] = firrtl.subfield %memory_rw(6) : (!firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, rdata flip: uint<17>, wmode: uint<1>, wdata: uint<17>, wmask: uint<17>>) -> !firrtl.uint<17>
|
||||
// CHECK: %[[v16:.+]] = firrtl.bitcast %14 : (!firrtl.bundle<a: uint<1>, b: uint<1>>) -> !firrtl.uint<2>
|
||||
// CHECK: %[[v17:.+]] = firrtl.bits %16 0 to 0 : (!firrtl.uint<2>) -> !firrtl.uint<1>
|
||||
// CHECK: %[[v18:.+]] = firrtl.cat %[[v17]], %[[v17]] : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<2>
|
||||
// CHECK: %[[v19:.+]] = firrtl.cat %[[v17]], %[[v18]] : (!firrtl.uint<1>, !firrtl.uint<2>) -> !firrtl.uint<3>
|
||||
// CHECK: %[[v24:.+]] = firrtl.cat %[[v17]], %[[v23:.+]] : (!firrtl.uint<1>, !firrtl.uint<7>) -> !firrtl.uint<8>
|
||||
// CHECK: %[[v25:.+]] = firrtl.bits %16 1 to 1 : (!firrtl.uint<2>) -> !firrtl.uint<1>
|
||||
// CHECK: %[[v26:.+]] = firrtl.cat %[[v25]], %[[v24]] : (!firrtl.uint<1>, !firrtl.uint<8>) -> !firrtl.uint<9>
|
||||
// CHECK: %[[v27:.+]] = firrtl.cat %[[v25]], %[[v26]] : (!firrtl.uint<1>, !firrtl.uint<9>) -> !firrtl.uint<10>
|
||||
// CHECK: %[[v28:.+]] = firrtl.cat %[[v25]], %[[v27]] : (!firrtl.uint<1>, !firrtl.uint<10>) -> !firrtl.uint<11>
|
||||
// CHECK: %[[v34:.+]] = firrtl.cat %[[v25]], %[[v33:.+]] : (!firrtl.uint<1>, !firrtl.uint<16>) -> !firrtl.uint<17>
|
||||
// CHECK: firrtl.strictconnect %[[v15]], %[[v34]] :
|
||||
// Ensure 0 bit fields are handled properly.
|
||||
%ram_MPORT = firrtl.mem Undefined {depth = 4 : i64, groupID = 1 : ui32, name = "ram", portNames = ["MPORT"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data: bundle<entry: bundle<a: uint<0>, b: uint<1>, c: uint<2>>>, mask: bundle<entry: bundle<a: uint<1>, b: uint<1>, c: uint<1>>>>
|
||||
// CHECK: %ram_MPORT = firrtl.mem Undefined {depth = 4 : i64, groupID = 1 : ui32, name = "ram", portNames = ["MPORT"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data: uint<3>, mask: uint<3>>
|
||||
|
||||
}
|
||||
|
||||
|
||||
firrtl.module @ZeroBitMasks(in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>, in %io: !firrtl.bundle<a: uint<0>, b: uint<20>>) {
|
||||
%invalid = firrtl.invalidvalue : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
%invalid_0 = firrtl.invalidvalue : !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
%ram_MPORT = firrtl.mem Undefined {depth = 1 : i64, groupID = 1 : ui32, name = "ram", portNames = ["MPORT"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>
|
||||
%3 = firrtl.subfield %ram_MPORT(3) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
firrtl.strictconnect %3, %invalid_0 : !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
%4 = firrtl.subfield %ram_MPORT(4) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
firrtl.strictconnect %4, %invalid : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: %ram_MPORT = firrtl.mem Undefined {depth = 1 : i64, groupID = 1 : ui32, name = "ram", portNames = ["MPORT"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: uint<20>, mask: uint<1>>
|
||||
// CHECK: %ram_MPORT_1 = firrtl.wire {name = "ram_MPORT"} : !firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>
|
||||
// CHECK: %[[v6:.+]] = firrtl.subfield %ram_MPORT_1(3) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
// CHECK: %[[v7:.+]] = firrtl.subfield %ram_MPORT(3) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: uint<20>, mask: uint<1>>) -> !firrtl.uint<20>
|
||||
// CHECK: %[[v8:.+]] = firrtl.bitcast %6 : (!firrtl.bundle<a: uint<0>, b: uint<20>>) -> !firrtl.uint<20>
|
||||
// CHECK: firrtl.strictconnect %7, %8 : !firrtl.uint<20>
|
||||
// CHECK: %[[v9:.+]] = firrtl.subfield %ram_MPORT_1(4) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: %[[v10:.+]] = firrtl.subfield %ram_MPORT(4) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: uint<20>, mask: uint<1>>) -> !firrtl.uint<1>
|
||||
// CHECK: %[[v11:.+]] = firrtl.bitcast %9 : (!firrtl.bundle<a: uint<1>, b: uint<1>>) -> !firrtl.uint<2>
|
||||
// CHECK: %[[v12:.+]] = firrtl.bits %11 0 to 0 : (!firrtl.uint<2>) -> !firrtl.uint<1>
|
||||
// CHECK: %[[v13:.+]] = firrtl.bits %11 1 to 1 : (!firrtl.uint<2>) -> !firrtl.uint<1>
|
||||
// CHECK: firrtl.strictconnect %[[v10]], %[[v13]] : !firrtl.uint<1>
|
||||
// CHECK: %[[v14:.+]] = firrtl.subfield %ram_MPORT_1(3) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
// CHECK: firrtl.strictconnect %[[v14]], %invalid_0 : !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
// CHECK: %[[v15:.+]] = firrtl.subfield %ram_MPORT_1(4) : (!firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<a: uint<0>, b: uint<20>>, mask: bundle<a: uint<1>, b: uint<1>>>) -> !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
firrtl.connect %3, %io : !firrtl.bundle<a: uint<0>, b: uint<20>>, !firrtl.bundle<a: uint<0>, b: uint<20>>
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
// RUN: circt-opt -pass-pipeline='firrtl.circuit(firrtl-lower-types)' %s | FileCheck --check-prefixes=CHECK,COMMON %s
|
||||
// RUN: circt-opt -pass-pipeline='firrtl.circuit(firrtl-lower-types{flatten-mem=true})' %s | FileCheck --check-prefix=FLATTEN %s
|
||||
// RUN: circt-opt -pass-pipeline='firrtl.circuit(firrtl-lower-types{preserve-aggregate=true})' %s | FileCheck --check-prefixes=AGGREGATE,COMMON %s
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -466,11 +466,14 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
|
|||
if (blackBoxMemory)
|
||||
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createBlackBoxMemoryPass());
|
||||
|
||||
if (replSeqMem)
|
||||
pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
|
||||
firrtl::createLowerMemoryPass());
|
||||
// The input mlir file could be firrtl dialect so we might need to clean
|
||||
// things up.
|
||||
if (lowerTypes) {
|
||||
pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypesPass(
|
||||
replSeqMem, preserveAggregate, preservePublicTypes));
|
||||
preserveAggregate, preservePublicTypes));
|
||||
// Only enable expand whens if lower types is also enabled.
|
||||
if (expandWhens) {
|
||||
auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
|
||||
|
|
|
|||
Loading…
Reference in New Issue