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[HW] Rename the 'parameters' member of hw.instance to 'oldParameters'. 

We're going to get a new model for parameters here and I want to make
room for it.  Both models will have to co-exist for a while.
This commit is contained in:
Chris Lattner 2021-09-18 14:57:42 -07:00
parent e97cff3fd5
commit a1e08007f0
8 changed files with 25 additions and 23 deletions
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14
include/circt/Dialect/HW/HWStructure.td
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@ -316,15 +316,17 @@ def InstanceOp : HWOp<"instance", [HasParent<"HWModuleOp">, Symbol,
let description = [{
This represents an instance of a module. The inputs and results are
the referenced module's inputs and outputs. The `argNames` and
`resultNames` attributes must match the referenced module. Any parameters
are stored in the `parameters` dictionary.
`resultNames` attributes must match the referenced module.
Any parameters in the "old" format (slated to be removed) are stored in the
`oldParameters` dictionary.
}];
let arguments = (ins StrAttr:$instanceName,
Confined<FlatSymbolRefAttr, [isModuleSymbol]>:$moduleName,
Variadic<AnyType>:$inputs,
StrArrayAttr:$argNames, StrArrayAttr:$resultNames,
OptionalAttr<DictionaryAttr>:$parameters,
OptionalAttr<DictionaryAttr>:$oldParameters,
OptionalAttr<SymbolNameAttr>:$sym_name);
let results = (outs Variadic<AnyType>);
@ -332,15 +334,15 @@ def InstanceOp : HWOp<"instance", [HasParent<"HWModuleOp">, Symbol,
/// Create a instance that refers to a known module.
OpBuilder<(ins "Operation*":$module, "StringAttr":$name,
"ArrayRef<Value>":$inputs,
CArg<"DictionaryAttr", "{}">:$parameters,
CArg<"DictionaryAttr", "{}">:$oldParameters,
CArg<"StringAttr", "{}">:$sym_name)>,
/// Create a instance that refers to a known module.
OpBuilder<(ins "Operation*":$module, "StringRef":$name,
"ArrayRef<Value>":$inputs,
CArg<"DictionaryAttr", "{}">:$parameters,
CArg<"DictionaryAttr", "{}">:$oldParameters,
CArg<"StringAttr", "{}">:$sym_name), [{
build($_builder, $_state, module, $_builder.getStringAttr(name), inputs,
parameters, sym_name);
oldParameters, sym_name);
}]>
];

8
lib/Dialect/ESI/ESIPasses.cpp
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@ -564,8 +564,8 @@ void ESIPortsPass::updateInstance(HWModuleOp mod, InstanceOp inst) {
// Clone the instance.
b.setInsertionPointAfter(inst);
DictionaryAttr parameters;
if (inst.parameters().hasValue())
parameters = inst.parameters().getValue();
if (inst.oldParameters().hasValue())
parameters = inst.oldParameters().getValue();
auto newInst = b.create<InstanceOp>(mod, inst.instanceNameAttr(), newOperands,
parameters, inst.sym_nameAttr());
@ -802,8 +802,8 @@ void ESIPortsPass::updateInstance(HWModuleExternOp mod, InstanceOp inst) {
// Create the new instance!
DictionaryAttr parameters;
if (inst.parameters().hasValue())
parameters = inst.parameters().getValue();
if (inst.oldParameters().hasValue())
parameters = inst.oldParameters().getValue();
InstanceOp newInst =
instBuilder.create<InstanceOp>(mod, inst.instanceNameAttr(), newOperands,

6
lib/Dialect/HW/HWOps.cpp
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@ -684,14 +684,15 @@ static LogicalResult verifyHWModuleGeneratedOp(HWModuleGeneratedOp op) {
/// Create a instance that refers to a known module.
void InstanceOp::build(OpBuilder &builder, OperationState &result,
Operation *module, StringAttr name,
ArrayRef<Value> inputs, DictionaryAttr parameters,
ArrayRef<Value> inputs, DictionaryAttr oldParameters,
StringAttr sym_name) {
assert(isAnyModule(module) && "Can only reference a module");
FunctionType modType = getModuleType(module);
build(builder, result, modType.getResults(), name,
FlatSymbolRefAttr::get(SymbolTable::getSymbolName(module)), inputs,
module->getAttrOfType<ArrayAttr>("argNames"),
module->getAttrOfType<ArrayAttr>("resultNames"), parameters, sym_name);
module->getAttrOfType<ArrayAttr>("resultNames"), oldParameters,
sym_name);
}
/// Lookup the module or extmodule for the symbol. This returns null on
@ -702,7 +703,6 @@ Operation *InstanceOp::getReferencedModule(const SymbolCache *cache) {
return result;
auto topLevelModuleOp = (*this)->getParentOfType<ModuleOp>();
return topLevelModuleOp.lookupSymbol(moduleName());
}

2
lib/Translation/ExportVerilog/ExportVerilog.cpp
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@ -2502,7 +2502,7 @@ LogicalResult StmtEmitter::visitStmt(InstanceOp op) {
indent() << prefix << verilogName.getValue();
// If this is a parameterized module, then emit the parameters.
if (auto paramDictOpt = op.parameters()) {
if (auto paramDictOpt = op.oldParameters()) {
DictionaryAttr paramDict = paramDictOpt.getValue();
if (!paramDict.empty()) {
os << " #(\n";

4
test/Conversion/FIRRTLToHW/lower-to-hw-module.mlir
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@ -65,7 +65,7 @@ firrtl.circuit "Simple" {
// Parameterized module reference.
// hw.instance carries the parameters, unlike at the FIRRTL layer.
// CHECK: %myext.out = hw.instance "myext" @MyParameterizedExtModule(in: %reset: i1) -> (out: i8) {parameters = {DEFAULT = 0 : i64, DEPTH = 3.242000e+01 : f64, FORMAT = "xyz_timeout=%d\0A", WIDTH = 32 : i8}}
// CHECK: %myext.out = hw.instance "myext" @MyParameterizedExtModule(in: %reset: i1) -> (out: i8) {oldParameters = {DEFAULT = 0 : i64, DEPTH = 3.242000e+01 : f64, FORMAT = "xyz_timeout=%d\0A", WIDTH = 32 : i8}}
%myext:2 = firrtl.instance @MyParameterizedExtModule {name = "myext", portNames=["in", "out"]}
: !firrtl.uint<1>, !firrtl.uint<8>
@ -142,7 +142,7 @@ firrtl.circuit "Simple" {
out %out0: !firrtl.uint<8>) {
// CHECK: %false = hw.constant false
// CHECK-NEXT: hw.instance "myext" @MyParameterizedExtModule(in: [[ARG:%.+]]: i1) -> (out: i8) {parameters
// CHECK-NEXT: hw.instance "myext" @MyParameterizedExtModule(in: [[ARG:%.+]]: i1) -> (out: i8) {oldParameters
%myext:2 = firrtl.instance @MyParameterizedExtModule {name = "myext", portNames=["in", "out"]}
: !firrtl.uint<1>, !firrtl.uint<8>

6
test/ExportVerilog/hw-dialect.mlir
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@ -199,9 +199,9 @@ hw.module @AB(%w: i1, %x: i1, %i2: i2, %i3: i0) -> (y: i1, z: i1, p: i1, p2: i1)
%w2 = hw.instance "a1" @AAA(d: %w: i1, e: %w1: i1) -> (f: i1)
%w1, %y = hw.instance "b1" @B(a: %w2: i1) -> (b: i1, c: i1)
%p = hw.instance "paramd" @EXT_W_PARAMS(a: %w: i1, b: %i3: i0) -> (out: i1) {parameters = {DEFAULT = 14000240888948784983 : i64, DEPTH = 3.242000e+01 : f64, FORMAT = "xyz_timeout=%d\0A", WIDTH = 32 : i8}}
%p = hw.instance "paramd" @EXT_W_PARAMS(a: %w: i1, b: %i3: i0) -> (out: i1) {oldParameters = {DEFAULT = 14000240888948784983 : i64, DEPTH = 3.242000e+01 : f64, FORMAT = "xyz_timeout=%d\0A", WIDTH = 32 : i8}}
%p2 = hw.instance "paramd2" @EXT_W_PARAMS2(a: %i2: i2) -> (out: i1) {parameters = {DEFAULT = 1 : i32}}
%p2 = hw.instance "paramd2" @EXT_W_PARAMS2(a: %i2: i2) -> (out: i1) {oldParameters = {DEFAULT = 1 : i32}}
hw.output %y, %x, %p, %p2 : i1, i1, i1, i1
}
@ -713,7 +713,7 @@ hw.module @Chi() -> (Chi_output : i0) {
// CHECK-NEXT: .Wtricky(40'd4294967295)
// CHECK-NEXT: ) bar ();
hw.instance "bar" @Bar1360() -> () {parameters = {WIDTH0 = 0 : i64, WIDTH1 = 4 : i4, WIDTH2 = 6812312123 : i40, WIDTH3 = -1 : si4, WIDTH4 = -88888888888888888 : si68, Wtricky = 4294967295 : i40}}
hw.instance "bar" @Bar1360() -> () {oldParameters = {WIDTH0 = 0 : i64, WIDTH1 = 4 : i4, WIDTH2 = 6812312123 : i40, WIDTH3 = -1 : si4, WIDTH4 = -88888888888888888 : si68, Wtricky = 4294967295 : i40}}
hw.output
}
hw.module.extern @Bar1360() attributes {verilogName = "RealBar"}

6
test/ExportVerilog/verilog-basic.mlir
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@ -301,11 +301,11 @@ hw.module @ExternMods(%a_in: i8) {
// CHECK: MyParameterizedExtModule #(
// CHECK: .CFG(FOO)
// CHECK: ) xyz2
hw.instance "xyz2" @MyParameterizedExtModule(in: %a_in: i8) -> (out: i1) {parameters = {CFG = #sv.verbatim.parameter<"FOO">}}
hw.instance "xyz2" @MyParameterizedExtModule(in: %a_in: i8) -> (out: i1) {oldParameters = {CFG = #sv.verbatim.parameter<"FOO">}}
// CHECK: MyParameterizedExtModule #(
// CHECK: .CFG("STRING")
// CHECK: ) xyz3
hw.instance "xyz3" @MyParameterizedExtModule(in: %a_in: i8) -> (out: i1) {parameters = {CFG = #sv.verbatim.parameter<"\"STRING\"">}}
hw.instance "xyz3" @MyParameterizedExtModule(in: %a_in: i8) -> (out: i1) {oldParameters = {CFG = #sv.verbatim.parameter<"\"STRING\"">}}
}
// CHECK-LABEL: module UseInstances
@ -324,7 +324,7 @@ hw.module @UseInstances(%a_in: i8) -> (a_out1: i1, a_out2: i1) {
// CHECK: .out (a_out2)
// CHECK: );
%xyz.out = hw.instance "xyz" @MyExtModule(in: %a_in: i8) -> (out: i1)
%xyz2.out = hw.instance "xyz2" @MyParameterizedExtModule(in: %a_in: i8) -> (out: i1) {parameters = {DEFAULT = 0 : i64, DEPTH = 3.500000e+00 : f64, FORMAT = "xyz_timeout=%d\0A", WIDTH = 32 : i8}}
%xyz2.out = hw.instance "xyz2" @MyParameterizedExtModule(in: %a_in: i8) -> (out: i1) {oldParameters = {DEFAULT = 0 : i64, DEPTH = 3.500000e+00 : f64, FORMAT = "xyz_timeout=%d\0A", WIDTH = 32 : i8}}
hw.output %xyz.out, %xyz2.out : i1, i1
}

2
test/ExportVerilog/verilog-errors.mlir
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@ -28,5 +28,5 @@ hw.module @A () {}
hw.module @B() {
// expected-error @+1 {{unknown parameter value 'width' = @Foo}}
hw.instance "foo" @A() -> () { parameters = { width = @Foo } }
hw.instance "foo" @A() -> () { oldParameters = { width = @Foo } }
}