Make this test print out the problem to the build log if there is one.

2021-08-15 16:08:58 -07:00 · 2021-08-15 16:08:58 -07:00 · 96d2c55530
parent fe91e0a29f
commit 96d2c55530
1 changed files with 2 additions and 1 deletions
--- a/integration_test/EmitVerilog/exampleCodeGen.fir
+++ b/integration_test/EmitVerilog/exampleCodeGen.fir
@ -1,6 +1,7 @@
 ; REQUIRES: verilator
 ; RUN: firtool -verilog -lower-to-hw %s > %t.sv
-; RUN: circt-rtl-sim.py %t.sv 2>&1 | grep PASS
+; RUN: circt-rtl-sim.py %t.sv 2>&1 | tee %t.out
+; RUN: grep PASS %t.out

 circuit top :
  module LFSR :