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[NFC] Add check for correct hw.module.generated in LowerToHW 

Add a check that the 3 memory tests generate generator modules.
This commit is contained in:
Andrew Lenharth 2021-09-13 09:57:44 -05:00
parent a3ed3e60c2
commit 9351492fc3
1 changed files with 21 additions and 0 deletions
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21
test/Conversion/FIRRTLToHW/lower-to-hw.mlir
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@ -6,6 +6,27 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
"sifive.enterprise.firrtl.ExtractAssertionsAnnotation", directory = "dir3", filename = "./dir3/filename3" }]}
{
//These come from MemSimple, IncompleteRead, and MemDepth1
// CHECK-LABEL: hw.generator.schema @FIRRTLMem, "FIRRTL_Memory", ["depth", "numReadPorts", "numWritePorts", "numReadWritePorts", "readLatency", "writeLatency", "width", "readUnderWrite"]
// CHECK-NEXT: hw.module.generated @FIRRTLMem_1_0_0_32_1_0_1_1,
// CHECK-SAME: @FIRRTLMem(%ro_clock_0: i1, %ro_en_0: i1, %ro_addr_0: i1) -> (ro_data_0: i32)
// CHECK-SAME: attributes {depth = 1 : i64, numReadPorts = 1 : ui32,
// CHECK-SAME: numReadWritePorts = 0 : ui32, numWritePorts = 0 : ui32,
// CHECK-SAME: readLatency = 0 : ui32, readUnderWrite = 1 : ui32,
// CHECK-SAME: width = 32 : ui32, writeLatency = 1 : ui32}
// CHECK-NEXT: hw.module.generated @FIRRTLMem_1_0_0_42_12_0_1_0,
// CHECK-SAME: @FIRRTLMem(%ro_clock_0: i1, %ro_en_0: i1, %ro_addr_0: i4) -> (ro_data_0: i42)
// CHECK-SAME: attributes {depth = 12 : i64, numReadPorts = 1 : ui32,
// CHECK-SAME: numReadWritePorts = 0 : ui32, numWritePorts = 0 : ui32,
// CHECK-SAME: readLatency = 0 : ui32, readUnderWrite = 0 : ui32,
// CHECK-SAME: width = 42 : ui32, writeLatency = 1 : ui32}
// CHECK-NEXT: hw.module.generated @FIRRTLMem_1_1_1_42_12_0_1_0,
// CHECK-SAME: @FIRRTLMem(%ro_clock_0: i1, %ro_en_0: i1, %ro_addr_0: i4, %rw_clock_0: i1, %rw_en_0: i1, %rw_addr_0: i4, %rw_wmode_0: i1, %rw_wmask_0: i1, %rw_wdata_0: i42, %wo_clock_0: i1, %wo_en_0: i1, %wo_addr_0: i4, %wo_mask_0: i1, %wo_data_0: i42) -> (ro_data_0: i42, rw_rdata_0: i42)
// CHECK-SAME: attributes {depth = 12 : i64, numReadPorts = 1 : ui32,
// CHECK-SAME: numReadWritePorts = 1 : ui32, numWritePorts = 1 : ui32,
// CHECK-SAME: readLatency = 0 : ui32, readUnderWrite = 0 : ui32,
// CHECK-SAME: width = 42 : ui32, writeLatency = 1 : ui32}
// CHECK-LABEL: hw.module @Simple
firrtl.module @Simple(in %in1: !firrtl.uint<4>,
in %in2: !firrtl.uint<2>,