[SV] Fixing broken integration test

Caused by changes to 'sv.always' by @lattner in 0f164dab5c.
2020-12-29 20:20:32 -08:00 · 2020-12-29 20:20:32 -08:00 · 92571eccc6
parent ea24cbeb88
commit 92571eccc6
1 changed files with 1 additions and 1 deletions
--- a/integration_test/EmitVerilog/basic.mlir
+++ b/integration_test/EmitVerilog/basic.mlir
@ -8,7 +8,7 @@ module {
  rtl.module @top(%clk: i1, %rstn: i1) {
    %c1 = rtl.instance "aaa" @AAA () : () -> (i1)
    %c1Shl = rtl.instance "shl" @shl (%c1) : (i1) -> (i1)
-    sv.alwaysat_posedge %clk {
+    sv.always posedge %clk {
      sv.fwrite "tick\n"
    }
  }