mirror of https://github.com/llvm/circt.git
[FIRRTL] Handle flipped bundle types in LowerTypes (#263)
The canonical representation of a BundleType with every field flipped is a FlipType that wraps the whole bundle. There were places where LowerTypes assumed a BundleType, which caused crashes for a FlipType wrapped around a BundleType. To address this: * LowerTypes will default to disabled in firtool, and can be enabled by passing the -enable-lower-types flag. * The instance op verifier was updated to guarantee the result type is a BundleType or a FlipType wrapped around a BundleType. * LowerTypes was updated to check for both scenarios in the places it previously assumed it was working with a BundleType.
This commit is contained in:
mikeurbach
GitHub
parent
5225d65e9f
commit
887513f8cb
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@ -56,6 +56,20 @@ static void flattenBundleTypes(FIRRTLType type, StringRef suffixSoFar,
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}
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}
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// Helper to peel off the outer most flip type from a bundle that has all flips
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// canonicalized to the outer level, or just return the bundle directly. For any
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// other type, returns null.
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static BundleType getCanonicalBundleType(Type originalType) {
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BundleType originalBundleType;
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if (auto flipType = originalType.dyn_cast<FlipType>())
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originalBundleType = flipType.getElementType().dyn_cast<BundleType>();
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else
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originalBundleType = originalType.dyn_cast<BundleType>();
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return originalBundleType;
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}
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//===----------------------------------------------------------------------===//
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// Pass Infrastructure
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//===----------------------------------------------------------------------===//
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@ -180,15 +194,20 @@ void FIRRTLTypesLowering::lowerArg(BlockArgument arg, FIRRTLType type) {
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// ensuring both lowerings are the same, we can process every module in the
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// circuit in parallel, and every instance will have the correct ports.
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void FIRRTLTypesLowering::visitDecl(InstanceOp op) {
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// The instance's ports are represented as one value with a bundle type.
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BundleType originalType = op.result().getType().cast<BundleType>();
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// The instance's ports are represented as one value with a bundle type. Due
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// to how bundles with flips are canonicalized, there may be an outer flip
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// type that wraps the whole bundle.
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Type originalType = op.result().getType();
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bool isFlip = originalType.isa<FlipType>();
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BundleType originalBundleType = getCanonicalBundleType(originalType);
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assert(originalBundleType && "instance result was not a bundle type");
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// Create a new, flat bundle type for the new result
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SmallVector<BundleType::BundleElement, 8> bundleElements;
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for (auto element : originalType.getElements()) {
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for (auto element : originalBundleType.getElements()) {
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// Flatten any nested bundle types the usual way.
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SmallVector<FlatBundleFieldEntry, 8> fieldTypes;
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flattenBundleTypes(element.second, element.first, false, fieldTypes);
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flattenBundleTypes(element.second, element.first, isFlip, fieldTypes);
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for (auto field : fieldTypes) {
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// Store the flat type for the new bundle type.
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@ -276,8 +295,13 @@ void FIRRTLTypesLowering::visitStmt(ConnectOp op) {
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Value dest = op.dest();
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Value src = op.src();
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// Attempt to get the bundle types, potentially unwrapping an outer flip type
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// that wraps the whole bundle.
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BundleType destType = getCanonicalBundleType(dest.getType());
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BundleType srcType = getCanonicalBundleType(src.getType());
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// If we aren't connecting two bundles, there is nothing to do.
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if (!dest.getType().isa<BundleType>() || !src.getType().isa<BundleType>())
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if (!destType || !srcType)
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return;
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// Get the lowered values for each side.
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@ -367,7 +391,8 @@ Value FIRRTLTypesLowering::getBundleLowering(Value oldValue,
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// field.
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void FIRRTLTypesLowering::getAllBundleLowerings(
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Value value, SmallVectorImpl<Value> &results) {
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BundleType bundleType = value.getType().cast<BundleType>();
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BundleType bundleType = getCanonicalBundleType(value.getType());
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assert(bundleType && "attempted to get bundle lowerings for non-bundle type");
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for (auto element : bundleType.getElements())
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results.push_back(getBundleLowering(value, element.first));
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}
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@ -523,13 +523,18 @@ static LogicalResult verifyInstanceOp(InstanceOp &instance) {
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return failure();
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}
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// Check that the result type is either a bundle type or a flip type that
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// wraps a bundle type.
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auto resultType = instance.getResult().getType().cast<FIRRTLType>();
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if (!resultType.isa<BundleType>()) {
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auto flipType = resultType.dyn_cast<FlipType>();
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if (!flipType || !flipType.getElementType().isa<BundleType>())
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return instance.emitOpError("has invalid result type of ") << resultType;
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}
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// Check that the result type is consistent with its module.
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if (auto referencedFModule = dyn_cast<FModuleOp>(referencedModule)) {
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auto bundle = instance.getResult()
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.getType()
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.cast<FIRRTLType>()
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.getPassiveType()
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.cast<BundleType>();
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auto bundle = resultType.getPassiveType().cast<BundleType>();
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auto bundleElements = bundle.getElements();
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size_t e = bundleElements.size();
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@ -290,4 +290,32 @@ firrtl.module @X(%a : !firrtl.uint<4>) {
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%0 = firrtl.bits %a 3 to 1 : (!firrtl.uint<4>) -> !firrtl.uint<2>
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}
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}
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}
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// -----
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firrtl.circuit "TopModule" {
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firrtl.module @SubModule(%a : !firrtl.uint<1>) {
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}
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firrtl.module @TopModule() {
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// expected-error @+1 {{'firrtl.instance' op has invalid result type of '!firrtl.uint<1>'}}
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%0 = firrtl.instance @SubModule : !firrtl.uint<1>
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}
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}
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// -----
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firrtl.circuit "TopModule" {
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firrtl.module @SubModule(%a : !firrtl.uint<1>) {
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}
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firrtl.module @TopModule() {
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// expected-error @+1 {{'firrtl.instance' op has invalid result type of '!firrtl.flip<uint<1>>'}}
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%0 = firrtl.instance @SubModule : !firrtl.flip<uint<1>>
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}
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}
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@ -1,4 +1,4 @@
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// RUN: circt-opt -pass-pipeline='firrtl.circuit(lower-firrtl-types)' %s | FileCheck %s
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// RUN: circt-opt -pass-pipeline='firrtl.circuit(lower-firrtl-types)' -split-input-file %s | FileCheck %s
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firrtl.circuit "TopLevel" {
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@ -30,32 +30,6 @@ firrtl.circuit "TopLevel" {
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}
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}
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// CHECK-LABEL: firrtl.module @Recursive
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// CHECK-SAME: %[[FLAT_ARG_1_NAME:arg_foo_bar_baz]]: [[FLAT_ARG_1_TYPE:!firrtl.uint<1>]]
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// CHECK-SAME: %[[FLAT_ARG_2_NAME:arg_foo_qux]]: [[FLAT_ARG_2_TYPE:!firrtl.sint<64>]]
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// CHECK-SAME: %[[OUT_1_NAME:out1]]: [[OUT_1_TYPE:!firrtl.flip<uint<1>>]]
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// CHECK-SAME: %[[OUT_2_NAME:out2]]: [[OUT_2_TYPE:!firrtl.flip<sint<64>>]]
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firrtl.module @Recursive(%arg: !firrtl.bundle<foo: bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>>,
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%out1: !firrtl.flip<uint<1>>, %out2: !firrtl.flip<sint<64>>) {
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// CHECK-NEXT: firrtl.connect %[[OUT_1_NAME]], %[[FLAT_ARG_1_NAME]] : [[OUT_1_TYPE]], [[FLAT_ARG_1_TYPE]]
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// CHECK-NEXT: firrtl.connect %[[OUT_2_NAME]], %[[FLAT_ARG_2_NAME]] : [[OUT_2_TYPE]], [[FLAT_ARG_2_TYPE]]
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%0 = firrtl.subfield %arg("foo") : (!firrtl.bundle<foo: bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>>) -> !firrtl.bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>
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%1 = firrtl.subfield %0("bar") : (!firrtl.bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>) -> !firrtl.bundle<baz: uint<1>>
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%2 = firrtl.subfield %1("baz") : (!firrtl.bundle<baz: uint<1>>) -> !firrtl.uint<1>
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%3 = firrtl.subfield %0("qux") : (!firrtl.bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>) -> !firrtl.sint<64>
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firrtl.connect %out1, %2 : !firrtl.flip<uint<1>>, !firrtl.uint<1>
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firrtl.connect %out2, %3 : !firrtl.flip<sint<64>>, !firrtl.sint<64>
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}
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// CHECK-LABEL: firrtl.module @Uniquification
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// CHECK-SAME: %[[FLATTENED_ARG:a_b]]: [[FLATTENED_TYPE:!firrtl.uint<1>]],
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// CHECK-NOT: %[[FLATTENED_ARG]]
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// CHECK-SAME: %[[RENAMED_ARG:a_b.+]]: [[RENAMED_TYPE:!firrtl.uint<1>]] {firrtl.name = "[[FLATTENED_ARG]]"}
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firrtl.module @Uniquification(%a: !firrtl.bundle<b: uint<1>>, %a_b: !firrtl.uint<1>) {
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}
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// CHECK-LABEL: firrtl.module @TopLevel
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// CHECK-SAME: %[[SOURCE_VALID_NAME:source_valid]]: [[SOURCE_VALID_TYPE:!firrtl.uint<1>]]
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// CHECK-SAME: %[[SOURCE_READY_NAME:source_ready]]: [[SOURCE_READY_TYPE:!firrtl.flip<uint<1>>]]
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@ -97,3 +71,76 @@ firrtl.circuit "TopLevel" {
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firrtl.connect %sink, %2 : !firrtl.bundle<valid: flip<uint<1>>, ready: uint<1>, data: flip<uint<64>>>, !firrtl.bundle<valid: uint<1>, ready: flip<uint<1>>, data: uint<64>>
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}
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}
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// -----
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firrtl.circuit "Recursive" {
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// CHECK-LABEL: firrtl.module @Recursive
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// CHECK-SAME: %[[FLAT_ARG_1_NAME:arg_foo_bar_baz]]: [[FLAT_ARG_1_TYPE:!firrtl.uint<1>]]
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// CHECK-SAME: %[[FLAT_ARG_2_NAME:arg_foo_qux]]: [[FLAT_ARG_2_TYPE:!firrtl.sint<64>]]
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// CHECK-SAME: %[[OUT_1_NAME:out1]]: [[OUT_1_TYPE:!firrtl.flip<uint<1>>]]
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// CHECK-SAME: %[[OUT_2_NAME:out2]]: [[OUT_2_TYPE:!firrtl.flip<sint<64>>]]
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firrtl.module @Recursive(%arg: !firrtl.bundle<foo: bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>>,
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%out1: !firrtl.flip<uint<1>>, %out2: !firrtl.flip<sint<64>>) {
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// CHECK-NEXT: firrtl.connect %[[OUT_1_NAME]], %[[FLAT_ARG_1_NAME]] : [[OUT_1_TYPE]], [[FLAT_ARG_1_TYPE]]
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// CHECK-NEXT: firrtl.connect %[[OUT_2_NAME]], %[[FLAT_ARG_2_NAME]] : [[OUT_2_TYPE]], [[FLAT_ARG_2_TYPE]]
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%0 = firrtl.subfield %arg("foo") : (!firrtl.bundle<foo: bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>>) -> !firrtl.bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>
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%1 = firrtl.subfield %0("bar") : (!firrtl.bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>) -> !firrtl.bundle<baz: uint<1>>
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%2 = firrtl.subfield %1("baz") : (!firrtl.bundle<baz: uint<1>>) -> !firrtl.uint<1>
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%3 = firrtl.subfield %0("qux") : (!firrtl.bundle<bar: bundle<baz: uint<1>>, qux: sint<64>>) -> !firrtl.sint<64>
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firrtl.connect %out1, %2 : !firrtl.flip<uint<1>>, !firrtl.uint<1>
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firrtl.connect %out2, %3 : !firrtl.flip<sint<64>>, !firrtl.sint<64>
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}
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}
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// -----
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firrtl.circuit "Uniquification" {
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// CHECK-LABEL: firrtl.module @Uniquification
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// CHECK-SAME: %[[FLATTENED_ARG:a_b]]: [[FLATTENED_TYPE:!firrtl.uint<1>]],
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// CHECK-NOT: %[[FLATTENED_ARG]]
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// CHECK-SAME: %[[RENAMED_ARG:a_b.+]]: [[RENAMED_TYPE:!firrtl.uint<1>]] {firrtl.name = "[[FLATTENED_ARG]]"}
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firrtl.module @Uniquification(%a: !firrtl.bundle<b: uint<1>>, %a_b: !firrtl.uint<1>) {
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}
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}
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// -----
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firrtl.circuit "InstanceFlipped" {
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firrtl.module @SubModule(%clock: !firrtl.clock, %reset: !firrtl.uint<1>) {
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}
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// CHECK-LABEL: firrtl.module @InstanceFlipped
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// CHECK: firrtl.instance @SubModule {{.*}} : !firrtl.flip<bundle<clock: clock, reset: uint<1>>>
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firrtl.module @InstanceFlipped(%clock: !firrtl.clock, %reset: !firrtl.uint<1>) {
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%int_bus = firrtl.instance @SubModule {name = "int_bus"} : !firrtl.flip<bundle<clock: clock, reset: uint<1>>>
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// CHECK: firrtl.subfield %int_bus("clock") {{.*}} -> !firrtl.flip<clock>
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%0 = firrtl.subfield %int_bus("clock") : (!firrtl.flip<bundle<clock: clock, reset: uint<1>>>) -> !firrtl.flip<clock>
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firrtl.connect %0, %clock : !firrtl.flip<clock>, !firrtl.clock
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// CHECK: firrtl.subfield %int_bus("reset") {{.*}} -> !firrtl.flip<uint<1>>
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%1 = firrtl.subfield %int_bus("reset") : (!firrtl.flip<bundle<clock: clock, reset: uint<1>>>) -> !firrtl.flip<uint<1>>
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firrtl.connect %1, %reset : !firrtl.flip<uint<1>>, !firrtl.uint<1>
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}
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}
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// -----
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firrtl.circuit "Top" {
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// CHECK-LABEL: firrtl.module @Top
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firrtl.module @Top(%in : !firrtl.bundle<a: uint<1>, b: uint<1>>,
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%out : !firrtl.flip<bundle<a: uint<1>, b: uint<1>>>) {
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// CHECK: firrtl.connect %out_a, %in_a : !firrtl.flip<uint<1>>, !firrtl.uint<1>
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// CHECK: firrtl.connect %out_b, %in_b : !firrtl.flip<uint<1>>, !firrtl.uint<1>
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firrtl.connect %out, %in : !firrtl.flip<bundle<a: uint<1>, b: uint<1>>>, !firrtl.bundle<a: uint<1>, b: uint<1>>
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}
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}
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@ -0,0 +1,17 @@
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// RUN: firtool %s -format=mlir -lower-to-rtl | circt-opt -verify-diagnostics | FileCheck %s --check-prefix=LOWER
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// RUN: firtool %s -format=mlir -lower-to-rtl -enable-lower-types | circt-opt -verify-diagnostics | FileCheck %s --check-prefix=LOWERTYPES
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firrtl.circuit "Top" {
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firrtl.module @Top(%in : !firrtl.bundle<a: uint<1>, b: uint<1>>,
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%out : !firrtl.bundle<a: flip<uint<1>>, b: flip<uint<1>>>) {
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firrtl.connect %out, %in : !firrtl.bundle<a: flip<uint<1>>, b: flip<uint<1>>>, !firrtl.bundle<a: uint<1>, b: uint<1>>
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}
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}
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// LOWER-LABEL: module attributes {firrtl.mainModule = "Top"}
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// expected-error: @+1 {{cannot lower this port type to RTL}}
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// LOWERTYPES-LABEL: module attributes {firrtl.mainModule = "Top"}
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// LOWERTYPES: %[[ARG0:.+]]: i1 {rtl.name = "in_a"}
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// LOWERTYPES: %[[ARG1:.+]]: i1 {rtl.name = "in_b"}
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// LOWERTYPES: rtl.output %[[ARG0]], %[[ARG1]]
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@ -54,6 +54,11 @@ static cl::opt<bool> disableOptimization("disable-opt",
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static cl::opt<bool> lowerToRTL("lower-to-rtl",
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cl::desc("run the lower-to-rtl pass"));
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static cl::opt<bool>
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enableLowerTypes("enable-lower-types",
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cl::desc("run the lower-types pass within lower-to-rtl"),
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cl::init(false));
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static cl::opt<bool>
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ignoreFIRLocations("ignore-fir-locators",
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cl::desc("ignore the @info locations in the .fir file"),
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@ -112,8 +117,9 @@ processBuffer(std::unique_ptr<llvm::MemoryBuffer> ownedBuffer,
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// Run the lower-to-rtl pass if requested.
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if (lowerToRTL) {
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pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
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firrtl::createLowerFIRRTLTypesPass());
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if (enableLowerTypes)
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pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
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firrtl::createLowerFIRRTLTypesPass());
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pm.addPass(firrtl::createLowerFIRRTLToRTLModulePass());
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pm.nest<rtl::RTLModuleOp>().addPass(firrtl::createLowerFIRRTLToRTLPass());
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}
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